• Title/Summary/Keyword: Fractional-order filter circuit

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Fractional-order LβCα Low-Pass Filter Circuit

  • Zhou, Rui;Zhang, Run-Fan;Chen, Di-Yi
    • Journal of Electrical Engineering and Technology
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    • v.10 no.4
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    • pp.1597-1609
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    • 2015
  • This paper introduces the fundamentals of the conventional LC low-pass filter circuit in the fractional domain. First, we study the new fundamentals of fractional-order LC low-pass filter circuit including the pure real angular frequency, the pure imaginary angular frequency and the short circuit angular frequency. Moreover, sensitivity analysis of the impedance characteristics and phase characteristics of the LC low-pass filter circuit with respect to the system variables is studied in detail, which shows the greater flexibility of the fractional-order filter circuit in designs. Furthermore, from the filtering property perspective, we systematically investigate the effects of the system variables (LC, frequency f and fractional orders) on the amplitude-frequency characteristics and phase-frequency characteristics. In addition, the detailed analyses of the cut-off frequency and filter factor are presented. Numerical experimental results are presented to verify the theoretical results introduced in this paper.

Design and fabrication of a novel multilayer bandpass filter with high-order harmonics suppression using parallel coupled microstrip filter

  • Fathi, Esmaeil;Setoudeh, Farbod;Tavakoli, Mohammad Bagher
    • ETRI Journal
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    • v.44 no.2
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    • pp.260-273
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    • 2022
  • This study presents a novel multilayer structure of parallel coupled-line bandpass filtercentered at 2.42 GHz with a fractional bandwidth value of approximately 19.4%. The designed filter can suppress harmonics with an appropriate frequency response by incorporating different techniques based on the multilayer technique. A combination of different techniques such as radial microstrip stubs and defected ground structure (DGS) and defected microstrip structure techniques are employed to suppress harmonics up to 5f0. These techniques are used in two layers to suppress up to 5f0. In addition, in this study, the effects of different parameters, such as the width of slot-line DGS, the angle of diagonal line slots in the upper layer, and the air gap between the two layers on the filter performance, are investigated. To verify the correct circuit operation, the designed filter is implemented and tested. The measurement results of the proposed filter are compared with the simulation results.

A Clock Regenerator using Two 2nd Order Sigma-Delta Modulators for Wide Range of Dividing Ratio

  • Oh, Seung-Wuk;Kim, Sang-Ho;Im, Sang-Soon;Ahn, Yong-Sung;Kang, Jin-Ku
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.1
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    • pp.10-17
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    • 2012
  • This paper presents a clock regenerator using two $2^{nd}$ order ${\sum}-{\Delta}$ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different ${\sum}-{\Delta}$ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 ${\mu}m$ CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.

Design of a CMOS Frequency Synthesizer for FRS Band (UHF FRS 대역 CMOS PLL 주파수 합성기 설계)

  • Lee, Jeung-Jin;Kim, Young-Sik
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.12
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    • pp.941-947
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    • 2017
  • This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

High-performance filtering power divider based on air-filled substrate integrated waveguide technology

  • Ali-Reza Moznebi;Kambiz Afrooz;Mostafa Danaeian
    • ETRI Journal
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    • v.45 no.2
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    • pp.338-345
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    • 2023
  • A filtering power divider based on air-filled substrate-integrated waveguide (AFSIW) technology is proposed in this study. The AFSIW structure is used in the proposed filtering power divider for substantially reducing the transmission losses. This structure occupies a large area because of the use of air as a dielectric instead of typical dielectric materials. A filtering power divider provides power division and frequency selectivity simultaneously in a single device. The proposed filtering power divider comprises three AFSIW cavities. The filtering function is achieved using symmetrical inductive posts. The input and output ports of the proposed circuit are realized by directly connecting coaxial lines to the AFSIW cavities. This transition from the coaxial line to the AFSIW cavity eliminates the additional transitions, such as AFSIW-SIW and SIW-conductor-backed coplanar waveguide, applied in existing AFSIW circuits. The proposed power divider with a second-order bandpass filtering response is fabricated and measured at 5.5 GHz. The measurement results show that this circuit has a minimum insertion loss of 1 dB, 3-dB fractional bandwidth of 11.2%, and return loss exceeding 11 dB.

A Design of the UWB Bandpass Filter with a Good Performance of the Stopband, and Notched Band in Passband (우수한 차단 대역 특성과 통과 대역 내에 저지 대역을 갖는 UWB 대역 통과 필터 설계)

  • An, Jae-Min;Kim, Yu-Seon;Pyo, Hyun-Seong;Lee, Hye-Sun;Lim, Yeong-Seog
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.1
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    • pp.28-35
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    • 2010
  • In this paper, we designed and fabricated a ultra-wideband(UWB) bandpass filter with a good performance of a stopband, and a notched band in passband. The transformed equivalent circuit of the highpass filter was realized by distributed element. A wide-passband with 3-dB fractional bandwidth of more than 100 % was achieved by using optimum response of the HPF. For improving lower and upper stopband characteristic, a cross coupling between feed lines was employed, which was analyzed by desegmentation technique. In order to reject interference of Wireless LAN and Hyper LAN(5.15~5.825 GHz), the narrow notched(rejection) band was realized by a spurline. The fabricated BPF indicated the passband from 3.1 to 10.55 GHz and the flat group delay of less than 0.94 ns over the entire passband except the rejection band. The filter shown sharp attenuation both inside and outside the band and notched band from 5.2 to 6.12 GHz.