• MALSORI
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• no.47
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• pp.85-96
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• 2003

It is difficult to implement sound field effect on real time using linear convolution in time domain because linear convolution needs much multiply operations. In this paper three ways is introduced to reduce multiplication operations. Firstly, linear convolution in time domain is replaced with circular convolution in frequency domain. It means that it operates multiplication in place of convolution. Secondly, one frame will be divided into several frames. It will reduce the multiplication operation in processing that transforms time domain into frequency domain. Finally, QFT will be used in place of FFT. Three ways result much reduction in multiplication operations. The reduction of the multiplication operation makes the real time implementation possible.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1221-1230
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• 1990

This paper presents a code generation method and an effective handling algorithm of ingeger constant multiplication for RISC machines in compiler design. As RISC Architectures usually use faster and more simply formed instructions than CISC's and most RISC processors do not have an integer multiplication instruction, it is required an effective algorithm to process integer multiplication. For the proposed code generator, Portable C Compiler(PCC) is redesigned to be suitable for an RISC machine, and composed an addition chain is built up to allow fast execution of constant multiplication, a part of integer one whicch appears very frequency in code generation phase.

• Current Optics and Photonics
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• v.5 no.4
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• pp.466-476
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• 2021

Frequency-multiplication technology based on microwave photonic principles can be used to generate microwave and millimeter wave signals with a wide frequency tuning range. However, the existing cascaded external modulation frequency-tupling scheme needs to ensure the phase coherence of the modulated Radio Frequency (RF) signal, while the phase modulation directly limits the frequency tuning range of the external modulation frequency multiplication. In this paper, a novel approach for generating an incoherent frequency 12-tupling signal with cascade modulation is proposed. The structure of cascaded dual-parallel Mach-Zehnder modulators can generate a frequency 12-tupling signal. The proposed structure uses no filter or phase control of the RF driving signal. Microwave photonic frequency-tupling was realized under incoherent conditions. Software simulations and experiments validated the proposed structure and proved that it can generate frequency 12-tupling microwave signals under incoherent conditions. Both the frequency range and reliability of the frequency-tupling system has been improved by the proposed structure.

• Journal of Elementary Mathematics Education in Korea
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• v.20 no.3
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• pp.407-430
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• 2016

In this study, we analyzed and discussed the instruction method of multiplication tables in mathematics textbooks from four countries in Asia; South Korea, China, Japan, and Singapore. The conclusions of remarks are states as follows: First. The teaching period and elements should be subdivided more structurally so that the learner could understand the concept and principle of multiplication tables better. Second. The bundle model, the linear model, and the array model of multiplication need to be presented so that the learners could experience various situations related to multiplication. Third, The concrete explanation and the higher frequency of presenting the commutative rules of multiplication is suggested so that the learner could understand the concept of the rules well. Fourth. The context related to multiplication by 1 and 0 should be presented so that the learner could comprehend the character of multiplication by 1 and 0. Fifth. The activities which helping memorizing a multiplication table should be suggested when the memorization is needed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.575-577
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• 2017

In public key cryptography such as RSA, modular exponentiation is the most time-consuming operation. RSA's modular exponentiation can be computed by repeated modular multiplication. To attain high efficiency for RSA, fast modular multiplication algorithms have been proposed to speed up decryption/encryption. Montgomery multiplication is limited by the carry propagation delay from the addition of long operands. In this paper, we propose a hardware structure that reduces the area of the Montgomery multiplication implementation for lightweight applications of RSA. Experimental results showed that the new design can achieve higher performance and reduce hardware area. A frequency of 884.9MHz and 250MHz were achieved with 84K and 56K gates respectively using the 90nm technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• MALSORI
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• no.51
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• pp.85-98
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• 2004

It is almost impossible to generate the sound field effect in real time with the time-domain linear convolution because of its large multiplication operation requirement. To solve this, three methods are introduced to reduce the number of multiplication operations in this paper. Firstly, the time-domain linear convolution is replaced with the frequency-domain circular convolution. In other words, the linear convolution result can be derived from that of the circular convolution. This technique reduces the number of multiplication operations remarkably, Secondly, a subframe concept is introduced, i.e., one original frame is divided into several subframes. Then the FFT is executed for each subframe and, as a result, the number of multiplication operations can be reduced. Finally, the QFT is used in stead of the FFT. By combining all the above three methods into our final the SFE generation algorithm, the number of computations are reduced sufficiently and the real-time SFE generation becomes possible with a general PC.

• Journal of IKEEE
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• v.24 no.4
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• pp.961-968
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• 2020

This paper describes a design of high performance modular multiplier that is essentially used for elliptic curve cryptography. Our modular multiplier supports modular multiplications for five field sizes over GF(p), including 192, 224, 256, 384 and 521 bits as defined in NIST FIPS 186-2, and it calculates modular multiplication in two steps with integer multiplication and reduction. The Karatsuba-Ofman multiplication algorithm was used for fast integer multiplication, and the Lazy reduction algorithm was adopted for reduction operation. In addition, the Nikhilam division algorithm was used for the division operation included in the Lazy reduction. The division operation is performed only once for a given modulo value, and it was designed to skip division operation when continuous modular multiplications with the same modulo value are calculated. It was estimated that our modular multiplier can perform 6.4 million modular multiplications per second when operating at a clock frequency of 32 MHz. It occupied 456,400 gate equivalents (GEs), and the estimated clock frequency was 67 MHz when synthesized with a 180-nm CMOS cell library.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1882-1889
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• 2021

This paper describes a high-performance hardware implementation of modular multiplication used as a core operation in elliptic curve cryptography. A 521-bit high-performance modular multiplier for NIST P-521 curve was designed by adopting 3-way Toom-Cook integer multiplication and fast reduction algorithm. Considering the property of the 3-way Toom-Cook algorithm in which the result of integer multiplication is multiplied by 1/3, modular multiplication was implemented on the Toom-Cook domain where the operands were multiplied by 3. The modular multiplier was implemented in the xczu7ev FPGA device to verify its hardware operation, and hardware resources of 69,958 LUTs, 4,991 flip-flops, and 101 DSP blocks were used. The maximum operating frequency on the Zynq7 FPGA device was 50 MHz, and it was estimated that about 4.16 million modular multiplications per second could be achieved.