• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.29-32
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• 2007

We analyzed the effect of cell resolution on the luminous efficacy through three-dimensional numerical simulation to understand the inherent discharge mechanism change in the plasma display panel. As the resolution increases from VGA to Full HD, the luminous efficacy decreases. With higher Xe content, VUV generation efficacy of Full HD becomes much lower than those of VGA or XGA cells, due to the increased plasma loss and lower electron heating. However a long electrode gap $140{\mu}m$ in Full HD cell with Ne-Xe [20%] results in the high luminous efficacy comparable to that of the XGA cell with $60{\mu}m$ gap. When comparing the effects of Xe content variation on the luminous efficacy of two different subpixel types, i. e., SDE (Segmented electrode in Delta color arrayed, Enclosed subpixel) [1] and conventional stripe barrier type in the XGA and Full HD cells, the luminous efficacy of SDE structure shows higher improvement in Full HD resolution compared with that of conventional type XGA cell, whose cause is identified as the reduced plasma loss.

• Journal of the Semiconductor & Display Technology
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• v.8 no.2
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• pp.59-62
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• 2009

In order to check the validation of LC simulation, 0.7 inch LCOS panel in full-HD resolution was fabricated and used for the electro-optical measurement. Compared the measured data with the calculated data, the averaged difference was 1.72% under 0 ~ +6 V bias on pixel electrode. To improve the optical characteristics of full-HD LCOS panel, the planar structure and trench structures (0.1 um, 0.2 um and 0.3 um-in-depth) between adjacent pixels were investigated with LC simulation. The planar structure showed the higher reflectance and faster reflectance-voltage response time than the trench structure. The optical fill factor and contrast ratio of planar structure were also higher than those of trench structures. As compared 1 um-in-depth trench structure resembled to the real structure with the planar structure, the optical fill factor was improved by 1.15% and the contrast ratio was improved by 5.26%. In order to minimize the loss of luminance and contrast ratio, the planar structure need to be applied between adjacent pixels.

• ETRI Journal
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• v.31 no.6
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

• Journal of Digital Contents Society
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• v.15 no.3
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• pp.425-432
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• 2014

4K high speed camera shooting enables shooting of fast subjects in Full HD 4 times resolution without motion blur due to increase in resolution and shutter speed. However, this shooting incurs several limitations including focus, intensity of radiation and increase in data quantity. As lack of intensity of radiation may occur due to increased shutter speed, it is shoot by opening aperture and limitation in focusing follows. In addition, there is limitation in shooting records since it has restriction in storage due to increased resolution and frame rate. In this regard, this study aims to analyze the limitations shown above through production case of 4K high speed camera (Phantom Flex 4K) and to design effective workflow to overcome this.

• Korean Journal of Agricultural and Forest Meteorology
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• v.12 no.1
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• pp.63-73
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• 2010

A comprehensive mapping project for agroclimatic zoning in South Korea will end by April 2010, which has required 4 years, a billion won (ca. 0.9 million US dollars) and 22 experts from 7 institutions to complete it. The map database from this project may be categorized into primary, secondary and analytical products. The primary products are called "high definition" digital climate maps (HD-DCMs) and available through the state of the art techniques in geospatial climatology. For example, daily minimum temperature surfaces were prepared by combining the climatic normals (1971-2000 and 1981-2008) of synoptic observations with the simulated thermodynamic nature of cold air by using the raster GIS and microwave temperature profiling which can quantify effects of cold air drainage on local temperature. The spatial resolution of the gridded climate data is 30m for temperature and solar irradiance, and 270m for precipitation. The secondary products are climatic indices produced by statistical analysis of the primary products and includes extremes, sums, and probabilities of climatic events relevant to farming activities at a given grid cell. The analytical products were prepared by driving agronomic models with the HD-DCMs and dates of full bloom, the risk of freezing damage, and the fruit quality are among the examples. Because the spatial resolution of local climate information for agronomic practices exceeds the current weather service scale, HD-DCMs and the value-added products are expected to supplement the insufficient spatial resolution of official climatology. In this lecture, state of the art techniques embedded in the products, how to combine the techniques with the existing geospatial information, and agroclimatic zoning for major crops and fruits in South Korea will be provided.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2013.10a
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• pp.763-764
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• 2013

A three-dimensional image capturing device and its signal processing algorithm and apparatus are presented. Three dimensional information is one of emerging differentiators that provides consumers with more realistic and immersive experiences in user interface, game, 3D-virtual reality, and 3D display. It has the depth information of a scene together with conventional color image so that full-information of real life that human eyes experience can be captured, recorded and reproduced. 20 Mega-Hertz-switching high speed image shutter device for 3D image capturing and its application to system prototype are presented[1,2]. For 3D image capturing, the system utilizes Time-of-Flight (TOF) principle by means of 20MHz high-speed micro-optical image modulator, so called 'optical resonator'. The high speed image modulation is obtained using the electro-optic operation of the multi-layer stacked structure having diffractive mirrors and optical resonance cavity which maximizes the magnitude of optical modulation[3,4]. The optical resonator is specially designed and fabricated realizing low resistance-capacitance cell structures having small RC-time constant. The optical shutter is positioned in front of a standard high resolution CMOS image sensor and modulates the IR image reflected from the object to capture a depth image (Figure 1). Suggested novel optical resonator enables capturing of a full HD depth image with depth accuracy of mm-scale, which is the largest depth image resolution among the-state-of-the-arts, which have been limited up to VGA. The 3D camera prototype realizes color/depth concurrent sensing optical architecture to capture 14Mp color and full HD depth images, simultaneously (Figure 2,3). The resulting high definition color/depth image and its capturing device have crucial impact on 3D business eco-system in IT industry especially as 3D image sensing means in the fields of 3D camera, gesture recognition, user interface, and 3D display. This paper presents MEMS-based optical resonator design, fabrication, 3D camera system prototype and signal processing algorithms.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.65-70
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• 2015

In this paper, we describe the world's first real-time ray-tracing chip architecture. Ray-tracing technology generates high-quality 3D graphics images better than current rasterization technology by providing four essential light effects: shadow, reflection, refraction and transmission. The real-time ray-tracing chip named RayChip includes a real-time ray-tracing graphics processing unit and an accelerating tree-building unit. An ARM Ltd. central processing unit (CPU) and other peripherals are also included to support all processes of 3D graphics applications. Using the accelerating tree-building unit named RayTree to minimize the CPU load, the chip uses a low-end CPU and decreases both silicon area and power consumption. The evaluation results with RayChip show appropriate performance to support real-time ray tracing in high-definition (HD) resolution, while the rendered images are scaled to full HD resolution. The chip also integrates the Linux operating system and the familiar OpenGL for Embedded Systems application programming interface for easy application development.

• Journal of the Institute of Convergence Signal Processing
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• v.16 no.1
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• pp.1-8
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• 2015

In many image processing tasks, connected component labeling (CCL) is performed to extract regions of interest. CCL was usually done in a sequential fashion when image resolution was relatively low and there are small number of input channels. As image resolution gets higher up to HD or Full HD and as the number of input channels increases, sequential CCL is too time-consuming to be used in real time applications. To cope with this situation, parallel CCL framework was introduced where multiple cores are utilized simultaneously. Several parallel CCL methods have been proposed in the literature. Among them are NSZ label equivalence (NSZ-LE) method[1], modified 8 directional label selection (M8DLS) method[2], and HYBRID1 method[3]. Soh [3] showed that HYBRID1 outperforms NSZ-LE and M8DLS, and argued that HYBRID1 is by far the best. In this paper we propose an improved hybrid parallel CCL algorithm termed as HYBRID2 that hybridizes M8DLS with label backtracking (LB) and show that it runs around 20% faster than HYBRID1 for various kinds of images.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.1
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• pp.28-34
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• 2015

Several parallelization methods that can be applied to High Efficiency Video Coding (HEVC) decoders are evaluated. The market requirements of high-resolution videos, such as Full HD and UHD, have been increasing. To satisfy the market requirements, several parallelization methods for HEVC decoders have been studied. Understanding these parallelization methods and objective comparisons of these methods are crucial to the real-time decoding of high-resolution videos. This paper introduces the parallelization methods that can be used in HEVC decoders and evaluates the parallelization methods comparatively. The experimental results show that the average speed-up factors of tile-level parallelism, wavefront parallel processing (WPP), frame-level parallelism, and 2D-wavefront parallelism are observed up to 4.59, 4.00, 2.20, and 3.16, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1685-1687
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• 2007

Excellent moving picture performance of plasma TV has been confirmed through the study and measurement using the method proposed by the APDC (Advanced PDP Development Center Corporation). Full-HD Plasma TVs with pixels of $1920{\times}1080[1]-[2]$, showed more than 900 TV-lines of resolution out of maximum scale of 1080, while typical LCD of the same pixel count showed only 1/3 of the plasma's performance. Moreover, even the latest 120Hz models of $1920{\times}1080$ LCD do not much PDPs with pixels of $1024{\times}768$, or $1366{\times}786$ in moving picture resolution. The measurement system proposed by the APDC showed very good agreement with subjective tests.