• 제목/요약/키워드: Functional verification

검색결과 330건 처리시간 0.022초

64비트 RISC 마이크로프로세서의 기능 검증에 관한 연구 (Functional Verification of 64bit RISC Microprocessor)

  • 김연선;서범수
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 1998년도 추계종합학술대회 논문집
    • /
    • pp.755-758
    • /
    • 1998
  • As the performance of microprocessor improves, the design complexity grows exponentially. Therefor, it is very important to make the bug-free model as early as possible in a design life-cycle. This paper describes the simulation-based functional verification methodology for the RTL level description model. It is performed by multi-stage verification methods using extensive hand-generated self-checking tests supplemented with random tests. This approach is opplied to the functional verification of the GPU processor of Raptor and various bugs are detected.

  • PDF

계층화된 테스트벤치를 이용한 검증 환경 구현 (Implementation of a Verification Environment using Layered Testbench)

  • 오영진;송기용
    • 융합신호처리학회논문지
    • /
    • 제12권2호
    • /
    • pp.145-149
    • /
    • 2011
  • 최근 시스템의 규모가 커지고 복잡해지면서, 시스템 수준에서의 기능 검증방법론이 중요해지고 있다. 기능블록의 검증을 위해서는 주로 BFM(bus functional model)이 사용되며, 기능 검증에 대한 부담이 증가할수록 올바른 검증환경 구성의 중요성은 더욱 증가한다. SystemVerilog는 Verilog HDL의 확장으로 하드웨어 설계언어의 특징과 검증언어의 특징을 동시에 갖는다. 동일한 언어로 설계기술, 기능 시뮬레이션 그리고 검증을 진행할 수 있다는 것은 시스템개발에서 큰 이점을 갖는다. 본 논문에서는 SystemVerilog를 이용하여 AMBA 버스와 기능블록으로 구성된 DUT를 설계하고, 계층적 테스트벤치를 이용한 검증환경에서 DUT의 가능을 검증한다. 기능 블록은 Adaptive FIR 필터와 Booth's 곱셈기를 사용한다. 이를 통하여 검증환경이 DUT와 연결되는 인터페이스의 부분적인 변경을 통하여 다른 하드웨어의 기능을 검증하는데 재사용되는 이점을 가지고 있음을 확인한다.

프로토콜 검증시스템의 설계 및 구현 (DESIGN AND IMPLEMENTATION OF A PROTOCOL VERIFICATION SYSTEM)

  • 김용진
    • ETRI Journal
    • /
    • 제11권4호
    • /
    • pp.22-36
    • /
    • 1989
  • In this paper, a design and implementation of an efficient protocol verification system named LOVE has been described. The LOVE has been developed specifically for LOTOS. It performs not only protocol syntax validation (PSV) but also protocol functional verification(PFV). The PSV is a test to check if a protocol is free from protocol syntax errors such as deadlocks and livelocks. The PFV confirms whether or not a protocol achieves its functional objectives. For the PSV, the reachability analysis is employed, and the observational equivalence test is used for the PFV. For protocol verification using the LOVE, a schematic protocol verification methodology has been outlined.

  • PDF

웹 기반 학습 시스템의 비기능 요구에 대한 구현 검증 기법 연구 (Verification Methods for the Implementation of Non-functional Requirements in Web-based Learning Systems)

  • 서동수;이혜리
    • 컴퓨터교육학회논문지
    • /
    • 제9권4호
    • /
    • pp.43-54
    • /
    • 2006
  • 웹 기반 학습 시스템의 사용자 요구는 일반적으로 기능 요구와 비기능 요구로 구분된다. 그 중 사용자가 원하는 품질 관련 비기능 요구는 개발자가 반드시 검증해야 할 주요 사항이지만 기능 요구와는 달리 확인 과정에 많은 어려움이 있었다. 본 논문은 웹 기반 학습 시스템의 개발에 적용할 수 있는 검증 기법으로서 품질 관련 비기능 요구사항이 적절히 구현되었는지를 검증하는 방법을 제안한다. 특히 효율성, 사용용이성과 같은 품질 요구가 설계에 영향을 주는 과정을 추적해 얻은 정보를 검증에 이용함으로써 이를 비기능 요구가 적절히 구현되었는지 확인할 수 있게 한다.

  • PDF

FUNCTIONAL VERIFICATION OF A SAFETY CLASS CONTROLLER FOR NPPS USING A UVM REGISTER MODEL

  • Kim, Kyuchull
    • Nuclear Engineering and Technology
    • /
    • 제46권3호
    • /
    • pp.381-386
    • /
    • 2014
  • A highly reliable safety class controller for NPPs (Nuclear Power Plants) is mandatory as even a minor malfunction can lead to disastrous consequences for people, the environment or the facility. In order to enhance the reliability of a safety class digital controller for NPPs, we employed a diversity approach, in which a PLC-type controller and a PLD-type controller are to be operated in parallel. We built and used structured testbenches based on the classes supported by UVM for functional verification of the PLD-type controller designed for NPPs. We incorporated a UVM register model into the testbenches in order to increase the controllability and the observability of the DUT(Device Under Test). With the increased testability, we could easily verify the datapaths between I/O ports and the register sets of the DUT, otherwise we had to perform black box tests for the datapaths, which is very cumbersome and time consuming. We were also able to perform constrained random verification very easily and systematically. From the study, we confirmed the various advantages of using the UVM register model in verification such as scalability, reusability and interoperability, and set some design guidelines for verification of the NPP controllers.

Development of ISO 26262 based Requirements Analysis and Verification Method for Efficient Development of Vehicle Software

  • Kyoung Lak Choi;Min Joong Kim;Young Min Kim
    • International Journal of Internet, Broadcasting and Communication
    • /
    • 제15권3호
    • /
    • pp.219-230
    • /
    • 2023
  • With the development of autonomous driving technology, as the use of software in vehicles increases, the complexity of the system increases and the difficulty of development increases. Developments that meet ISO 26262 must be carried out to reduce the malfunctions that may occur in vehicles where the system is becoming more complex. ISO 26262 for the functional safety of the vehicle industry proposes to consider functional safety from the design stage to all stages of development. Specifically at the software level, the requirements to be complied with during development and the requirements to be complied with during verification are defined. However, it is not clearly expressed about specific design methods or development methods, and it is necessary to supplement development guidelines. The importance of analysis and verification of requirements is increasing due to the development of technology and the increase of system complexity. The vehicle industry must carry out developments that meet functional safety requirements while carrying out various development activities. We propose a process that reflects the perspective of system engineering to meet the smooth application and developmentrequirements of ISO 26262. In addition, the safety analysis/verification FMEA processforthe safety of the proposed ISO 26262 function was conducted based on the FCAS (Forward Collision Avoidance Assist System) function applied to autonomous vehicles and the results were confirmed. In addition, the safety analysis/verification FMEA process for the safety of the proposed ISO 26262 function was conducted based on the FCAS (Forward Collision Avoidance Assist System) function applied to the advanced driver assistance system and the results were confirmed.

Dosimetric Verification for Primary Focal Hypermetabolism of Nasopharyngeal Carcinoma Patients Treated with Dynamic Intensity-modulated Radiation Therapy

  • Xin, Yong;Wang, Jia-Yang;Li, Liang;Tang, Tian-You;Liu, Gui-Hong;Wang, Jian-She;Xu, Yu-Mei;Chen, Yong;Zhang, Long-Zhen
    • Asian Pacific Journal of Cancer Prevention
    • /
    • 제13권3호
    • /
    • pp.985-989
    • /
    • 2012
  • Objective: To make sure the feasibility with $^{18F}FDG$ PET/CT to guided dynamic intensity-modulated radiation therapy (IMRT) for nasopharyngeal carcinoma patients, by dosimetric verification before treatment. Methods: Chose 11 patients in III~IVA nasopharyngeal carcinoma treated with functional image-guided IMRT and absolute and relative dosimetric verification by Varian 23EX LA, ionization chamber, 2DICA of I'mRT Matrixx and IBA detachable phantom. Drawing outline and making treatment plan were by different imaging techniques (CT and $^{18F}FDG$ PET/CT). The dose distributions of the various regional were realized by SMART. Results: The absolute mean errors of interest area were $2.39%{\pm}0.66$ using 0.6cc ice chamber. Results using DTA method, the average relative dose measurements within our protocol (3%, 3 mm) were 87.64% at 300 MU/min in all filed. Conclusions: Dosimetric verification before IMRT is obligatory and necessary. Ionization chamber and 2DICA of I'mRT Matrixx was the effective dosimetric verification tool for primary focal hyper metabolism in functional image-guided dynamic IMRT for nasopharyngeal carcinoma. Our preliminary evidence indicates that functional image-guided dynamic IMRT is feasible.

마이크로프로세서를 위한 효율적인 기능 검증 환경 구현 (An Implementation of Efficient Functional Verification Environment for Microprocessor)

  • 권오현;이문기
    • 대한전자공학회논문지SD
    • /
    • 제41권7호
    • /
    • pp.43-52
    • /
    • 2004
  • 본 논문은 마이크로프로세서의 설계과정 중, 중요도가 크게 부각되고 있는 기능 검증을 좀더 효율적으로 할 수 있는 검증환경을 제안한다. 본 검증 환경은 테스트 벡터 생성부분, 시뮬레이션 부분, 결과 비교 부분으로 구성되어 있다. 기존에 사용되던 검증 방법보다 좀더 효율적인 기능 검증이 가능하도록 하기 위해 바이어스 랜덤 테스트 벡터 생성기를 사용하였고, 참조모델로 재정의 가능 명령어 수준 시뮬레이터를 사용하였다. 본 검증 환경에서 수행된 결과를 비교함으로써 일반적인 테스트벡터에서 발견하기 어려운 오류 유형을 발견하고 새로운 오류 유형의 기준을 제시하는 효과를 지닌다.

SoC Front-end 설계를 위한 통합 환경

  • 김기선;김성식;이희연;김기현;채재호
    • 전자공학회지
    • /
    • 제30권9호
    • /
    • pp.1002-1011
    • /
    • 2003
  • In this paper, we introduce an integrated SoC front-end design & verification environment which can be practically used in the embedded 32-bit processor-core SoC VLSI design. Our introduced SoC design & verification environment integrates two most important flows, such as the RTL power estimation and code coverage analysis, with the functional verification (chip validation) flow which is used in the conventional simulation-based design. For this, we developed two simulation-based inhouse tools, RTL power estimator and code coverage analyzer, and used them to adopt them to our RTL design and to increase the design quality of that. Our integrated design environment also includes basic design and verification flows such as the gate-level functional verification with back annotation information and test vector capture & replay environment.

  • PDF

해양플랜트 유지보수장치 엔지니어링을 위한 장비 배치 검증수행모델에 관한 연구 (A Study on the Model of Equipment Layout Verification for Offshore Plant Maintenance Equipment Engineering)

  • 한성종;박범
    • 플랜트 저널
    • /
    • 제13권4호
    • /
    • pp.41-47
    • /
    • 2017
  • 본 논문은 해양플랜트 입찰단계에서 시스템엔지니어링(Systems Engineering)기법을 이용하여 해양플랜트를 구성하고 있는 장비 배치를 검증(Verification)할 수 있는 검증수행모델에 대한 연구이다. 해양플랜트 상부구조물(Topside) 유지보수 장비들을 엔지니어링하기 위하여는 Topside 장비 Layout검증이 선행되어야 한다. 하지만 입찰단계에서 완성도가 높지않는 FEED(Front End Engineering Design)결과물로 인한 많은 오류가 존재함에도 불구하고 검토시간의 부족 등의 이유로 검증을 수행하지 못하는 경우가 존재한다. 따라서 본 논문에서는 다학제간 접근방식인 시스템엔지니어링 프로세스를 간략화하여 적용함으로써 제한된 시간내 효과적으로 장비배치를 검증할 수 있는 검증수행모델을 제안하였다. 모델의 구성은 기능전개모델(Functional Deployment Model)을 통하여 구축하였으며 사례연구를 통하여 본 Topside 장비 배치에 대한 검증 수행모델을 검증하였다.

  • PDF