• Journal of the Korea Institute of Military Science and Technology
• /
• v.13 no.3
• /
• pp.378-387
• /
• 2010

In this paper, we present new structure of wideband parabolic gain equalizer for TWT applied to printed circuit board. The gain equalizer is manufactured by using design variables of transmission line obtained from derived formulae. We compared the test results of two equalizers(reference equalizer and our equalizer). From that, we confirmed the validity of presented method. The presented equalizer is 1/3 times lighter, 1/2.7 times smaller and 1/10 times chipper than those of reference equalizer(Inmet company), respectively.

• Journal of the Optical Society of Korea
• /
• v.4 no.1
• /
• pp.14-18
• /
• 2000

We have investigated gain flattening of EDFA systems with or without a gain equalizer for WDM long-haul transmission using a re-circulating EDFA loop. Without a gain equalizer, gain variation as small as 2.9 dB was achieved over the 10-nm band of a 100 cascaded EDFA system by the inversion principle. With a gain equalizer based on all-fiber acousto-optic tunable filters, two different config-urations of EDFAs were tested. For a single-stage EDFA scheme, the 21-nm band has shown 3.8 dB of gain variation at 17.4 ∼ 20.3 dB of OSNRs after the 100the stage of EDFAs. For a dual-stage EDFA scheme, a wider bandwidth of 34 nm has shown 3.6-dB variation after 40 cascaded EDFAs.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.41 no.4
• /
• pp.131-139
• /
• 2004

This paper proposes a variable-Q digital graphic equalizer with the opposite filters. A method for designing the proposed equalizer is also presented. In the proposed variable-Q equalizer, we adjust the Q-factor of the equalizer filter depending on the gain, yielding an improved equalizer performance. Also, by increasing the Q-factor of the opposite filters gracefully as the gain becomes greater, the inter-band interference can be removed effectively. We shall show that the frequency response of the proposed equalizer can reproduce the user's gain setting faithfully.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.11
• /
• pp.635-639
• /
• 2016

In the devices used in the microwave frequency band, the gain decreases as the frequency increases due to the parasitic component. To compensate for these characteristics, a linear gain equalizer with an opposite slope is needed in wideband systems, such as those used for electronic warfare. In this study, a linear gain equalizer that can be used in the 18 ~ 40GHz band is designed and fabricated. Circuit design and momentum design (optimizations) were carried out to reduce the errors between design and manufacturing. A thin film process is used to minimize the parasitic components within the implementation frequency band. A sheet resistance of 100 ohm/square was employed to minimize the wavelength variation due to the length of the thin film resistor. This linear gain equalizer is a structure that combines a quarter wavelength-resonator on a series microstrip line with a resistor. All three 1/4 wavelength short resonators were used. The fabricated linear gain equalizer has a loss of more than -5dB at 40GHz and a 6dB slope in the 18 ~ 40GHz band. By using the manufactured gain equalizer in a multi-stage connected device such as an electronic warfare receiver, the gain flatness degradation with increasing frequency can be reduced.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.64-70
• /
• 2009

A 6-Gbps feed-forward equalizer having a 6.2-dB gain at 3GHz is designed in 0.13-um CMOS technology and the equalizer helps error-free data recovery over a 7-m SATA cable with 14.7dB loss. Based on a differentially-connected varactor, the proposed equalizer uses only a one-fourth varactor size of a conventional equalizer, which enables the equalizer's integration in a pad-frame, high operating frequency, and low power dissipation of 3.6mW.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.4
• /
• pp.405-410
• /
• 2012

This paper presents an inductorless 8-Gb/s adaptive passive equalizer with low-power consumption and small chip area. The equalizer has a tunable RC filter which provides high-frequency gain boosting and a limiting amplifier that restores the signal level from the filter output. It also includes a feedback loop which automatically adjusts the filter gain for the optimal frequency response. The equalizer fabricated in $0.18-{\mu}m$ CMOS technology can successfully equalize 8-Gb/s data transmitted through up to 50-cm FR4 PCB channels. It consumes 6.75 mW from 1.8-V supply voltage and occupies $0.021mm^2$ of chip area.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.45 no.10
• /
• pp.59-64
• /
• 2008

In this paper an adjustable linear gain equalizer which is operated from 6GHz to 18GHz in order to apply wideband RF circuit System is proposed and fabricated on $Al_2O_3$ substrate using thin film process. An adjustable linear gain equalizer is proposed to T type circuit and designed to aim on variable slope $-7dB{\sim}-13dB$ using the PIN Diode

• Journal of information and communication convergence engineering
• /
• v.8 no.3
• /
• pp.258-262
• /
• 2010

This paper represents design broadband impedance matching circuit for Coupler to improve power transfer efficiency in the broadband power line communication(BPLC) systems. The Butterworth gain function equalizer is used to design broadband matching circuit. A practical PLC Coupler impedance matching circuit is designed, and the characteristics for S11 and S21 of PLC Coupler are enhanced comparing with unmatched one. This is done by maximizing the power transfer gain from modem to the load.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.9
• /
• pp.54-61
• /
• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Journal of the Korea Computer Industry Society
• /
• v.3 no.1
• /
• pp.27-34
• /
• 2002

There is much interest on information communications owing to the rapid development of network and IT(Information Technology). Analog signals are converted into digital signals for information communications. However, it is very difficult to completely erase the distortion induced during the conversion of analog signals such as voices and images into digital signals. Existing audio graphic equalizer requires very complex processes to calculate the gain and coefficients of the higher-order filter which is required to generate natural sound and to satisfy the need of each person. Unfortunately it is uneconomical and very difficult to embed the existing digital audio equalizer in the system because of the complexity of the existing digital audio equalizer for high quality sound. This paper discusses the design of a new digital audio graphic equalizer(DAGEQ) which can improve system performance and the quality of audio sound, and can be embedded in the system. This new DAGEQ is designed so that the gain can be controlled automatically. The automatic control of coefficients and gain empowers real time processing and the improvement of audio quality.