• Title/Summary/Keyword: Gigabit Ethernet

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Design and Implementation of 10Gigabit Ethernet Frame Multiplexer/Demultiplexer (10기가비트 이더넷 프레임 다중화/역다중화기 설계 및 구현)

  • 최창호;주범순;김도연;정해원
    • Proceedings of the IEEK Conference
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    • 2003.07a
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    • pp.378-381
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    • 2003
  • This paper presents a design and implementation of 10gigabit ethernet frame multiplexer/demultiplexer. In this paper, we discuss gigabit and 10 gigabit ethernet standard interfaces(GMII/XGMII) and we propose multiple gigabit ethernet frame multiplexing/demultiplexing scheme to handle 10gigabit ethernet frame instead of using 10gigabit network processor. And then 10gigabit ethernet frame MUX/DMUX is designed, verified and implemented using FPGA.

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A traffic analysis of Gigabit Ethernet high-speed network design (초고속 네트워크 구현을 위한 Gigabit Ethernet 트래픽 분석)

  • 서석철;고남영
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.1
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    • pp.48-54
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    • 2002
  • Gigabit Ethernet was advented as Internet's activation from owing to Internet user and the development of its various application and as inevitability the high-speed network as its demand for more and more the bandwidth by much application using the network. This Gigabit Ethernet makes an alternative plan to solve the request traffic by Internet user, because it holds several merits as providing great capacity with the network in the existing Ethernet environment and as displaying highly efficient ability This paper researches into a concept and characters about Gigabit Ethernet technology and raises the stability and efficiency of Gigabit Ethernet with regard of competing against FDDI technology and using Traffic analysis.

Design and Implementation of 10Gigabit Ethernet System with IPC and Frame MUX/DEMUX Architecture (10기가비트 이더넷 인터페이스를 위한 프레임 다중화기/역다중화기와 IPC를 갖는 10기가비트 이더넷 시스템의 설계 및 구현)

  • 조규인;김유진;정해원;조경록
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.5
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    • pp.27-36
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    • 2004
  • In this paper, we propose the ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame multiplex/demultiplexer architecture for the edge switch system based on Linux that has 10 Gigabit Ethernet (10Gigabit Ethernet) port with 72Gbps capacities. we discuss the ethernet IPC with ethernet switch and we propose design and implementation of ethernet Inter-Processor Communication (IPC) network architecture and multiple gigabit ethernet frame rnultiplexing/demultiplexing scheme to handle 10gigabit ethernet frame instead of using 10gigabit network processor. And then ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame MUX/DMUX architecture is designed verified and implemented.

The analysis of Link efficiency of Gigabit Ethernet with simulation (Simulation을 통한 Gigabit Ethernet의 링크효율 분석)

  • 전찬욱;오대호;서석철;이재완;고남영
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.05a
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    • pp.125-129
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    • 2002
  • In the multimedia age, the development of Internet/Intranet circumstances makes Required Traffic per user be gradually larger. And the more demand getting many pieces of information quickly increases, the more required the rapid network is as a necessary consequence. This is why we need the advanced Ethernet. Gigabit Ethernet has many advantages in many respects. For example, it increases the capacity of network and makes network highly efficient in the existing Ethernet circumstance. Thus, Gigabit Ethernet becomes a counterproposal that can resolve Required Traffic per internet user. Present study inquires the concepts and the characteristics connected with Gigabit Ethernet Technology and analyses the Link efficiency with a hypothetical modeling.

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Minimum Bandwidth Clock Recovery Algorithm for 10 Gigabit Ethernet (10 Gigabit Ethernet을 위한 최소 대역폭 클럭리커버리 알고리즘)

  • 성충환;전경규;김환우;김대영
    • Proceedings of the IEEK Conference
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    • 2001.09a
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    • pp.911-914
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    • 2001
  • 본 논문에서는 10Gigabit Ethernet 물리계충 전송 기술로서 IEEE 802.3 Higher Speed Study Group (HSSG)에서 검토했던 방법으로 선로부호화 방법이 있는데 그 중에서 국내 연구진에 의해 제안된 최소 대역폭 선로부호 MB810을 사용하여 10Gigabit Ethernet에서의 clock recovery 가능성에 대해 알아 본다. MB810 code를 사용하면 기존의 통신 시스템에서 필요로하는 대역폭을 반만 사용하여 전송할 수 있기 때문에 대역 효율이 좋아지나 이전의 일반적인 square law 방법으로는 clock recovery가 어렵다. 본 논문에서는 4th power law 방법을 사용했을때의 이론적인 해석과 시뮬레이션 결과를 보인다.

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Gigabit Ethernet PON(Passive Optical Network) Link Protection (Gigabit Ethernet PON(Passive Optical Network) 링크 이중화)

  • 이민효;민성기
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.04a
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    • pp.427-429
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    • 2004
  • 최근 광대역 멀티미디어 서비스에 대한 관심이 HD(High Density)방송의 시작과 함께 고조되고 있다. WPEG(Moving Picture Experts Group) HD 방송 채널을 수용하기 위해서 요구되는 방송대역은 20Mbps로 현재 가입자 망으로 한계를 가지고 있다. 궁극적인 해결 방안으로 FTTH(Fiber To The Hone) 광 가입자망이 논의되고 있다. 광 가입자 망의 유력한 방법중의 하나가 Gigabit Ethernet PON으로 IEEE(Institute of Electrical and Electronics) 802.3 EFH(Ethernet First Mile) AH Group을 중심으로 표준화 진행 중에 있다. IEEE 802.3 EFM AH Group에서는 가입자 망 장애에 대한 Protection 링크 이중화가 고려되고 있지 않아 본 논문에서 Gigabit Ethernet PON에서 링크 이중화 방법을 제시 하고자 한다.

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Gigabit Ethemet Upstream Transmission over WDM-PON Employing Remotely Wavelength-Locked Fabry-Perot Lasers (WDM-PON에서 원격으로 파장 고정된 Fabry-Perot 레이저를 사용한 Gigabit Ethernet 상향 신호 전송)

  • Kim Hyun Deok
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.15 no.12 s.91
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    • pp.1207-1215
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    • 2004
  • A Gigabit Ethernet upstream transmission over a WDM-PON employing remotely wavelength-locked Fabry-Perot lasers has been demonstrated. We have successfully demonstrated a WDM transmission of four Gigabit Ethernet channels with 100 GHz channel spacing over 30 km conventional single mode fiber. The measured f-factor was larger than 17.1 dB. We have also investigated the beating noise characteristics of a wavelength-locked Fabry-Perot laser and showed the remotely wavelength-locked Fabry-Perot laser suppresses the intensity noise of the incoherent light injected, which cause a 6.3 dB SNR improvement compared with that of the conventional spectrum-sliced light source.

Practical MAC address table lookup scheme for gigabit ethernet switch (기가비트 이더넷 스위치에서 빠른 MAC 주소 테이블의 검색 방법)

  • 이승왕;박인철
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.799-802
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    • 1998
  • As we know, gigabit ethernet is a new technology to be substituted for current fast ethernet used widely in local area network. The switch used in gigabit ethernet should deal with frames in giga-bps. To do such a fast switching, we need that serveral processes meet the budgets, such as MAC address table lookup, several giga speed path setup, fast scheduling, and etc. Especially MAC address table lookup has to be processed in the same speed with speed of incoming packets, thus the bottleneck in the process can cause packet loss by the overflow in the input buffer. We devise new practical hardware hashing method to perform fast table lookup by minimizing the number of external memory access and accelerating with hardware.

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M-VIA Implementation on a Gigabit Ethernet Card (기가비트 이더넷상에서의 M-VIA 구현)

  • 윤인수;정상화
    • Journal of KIISE:Computer Systems and Theory
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    • v.29 no.12
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    • pp.648-654
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    • 2002
  • The Virtual Interface Architecture(VIA) is an industry standard for communication over system area networks(SANs). M-VIA is a software implementation of VIA technology on Linux. In this paper, we implemented the M-VIA on an AceNIC Gigabit Ethernet by developing a new AceNIC driver for the M-VIA. We analyzed the M-VIA data segmentation processes. When a Gigabit Ethernet MTU is larger than 1514 bytes, M-VIA data segmentation size leaves much room for improvement. So we experimented with various MTU and M-VIA data segmentation size and compared the performances.

Implementation of Gigabit Ethernet Line Interface Controller using Network Processor (네트워크 프로세서를 이용한 기가비트 이더넷 라인 정합 제어기 구현)

  • 김용태;이강복;이형섭
    • Proceedings of the IEEK Conference
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    • 2002.06a
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    • pp.359-362
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    • 2002
  • In this paper, we propose a structure of 800bps high speed router and a gigabit Ethernet line interface board. Having Programmability, network processor is applied to gjgabit Ethernet line interface board. Also, we propose a new method to upgrade image files that consist of operating system and drivers. It is possible to upgrade image files for several boards at once and to reduce the elapsed time for image upgrade using tile proposed method.

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