• Journal of information and communication convergence engineering
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• v.3 no.1
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• pp.28-32
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• 2005

In this paper, we propose a novel test method to effectively detect hard and soft faults in CMOS 2-stage op-amps. The proposed method uses a very high frequency sinusoidal signal that exceeds unit gain bandwidth to maximize the fault effects. Since the proposed test method doesn't require any complex algorithms to generate the test pattern and uses only a single test pattern to detect all target faults, therefore test costs can be much reduced. The area overhead is also very small because the CUT is converted to a unit gain amplifier. Using HSPICE simulation, the results indicated a high degree of fault coverage for hard and soft faults in CMOS 2-stage op-amps. To verify this proposed method, we fabricated a CMOS op-amp that contained various short and open faults through the Hyundai 0.65-um 2-poly 2-metal CMOS process. Experimental results for the fabricated chip have shown that the proposed test method can effectively detect hard and soft faults in CMOS op-amps.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.819-822
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• 1998

The high complexity of digital circuits has changed the digital circuits design mehtods from schemeatic-based to hardware description languages like VHDL, verilog that make hardware faults become more hard to detect. Thus test generation to detect hardware defects is very important part of the design. But most of the test generation methods are gate-level based. In this paper new high-level test generation method to detect stuck-at-faults on gate level is described. This test generation method is independent of synthesis results and reduce the time and efforts for test generation.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.1
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• pp.23-28
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• 2009

Testing of analog(and mixed-signal) circuits has been a difficult task for test engineers and effective test techniques to solve these problems are required. This paper develops a new technique which increases fault detection and diagnosis rates for analog circuits by using extended MTSS (Modified Time Slot Specification) technique based on MTSS proposed by the author. High performance current sensors with digital outputs are used as core components for these techniques. A fault diagnosis structure with minimal hardware overhead in ATE is also described.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.313-318
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• 2012

This paper presents an automatic system to detect variety of faults from fine pitch COF(chip-on-film) which is less than $30{\mu}m$. Developed system contains circuits and technique to detect fast various faults such as hard open, hard short, soft open and soft short from fine pattern. Basic principle for fault detection is to monitor fine differential voltage from pattern resistance differences between fault-free and faulty cases. The technique uses also radio frequency resonator arrays for easy detection to amplify fine differential voltage. We anticipate that proposed system is to be an alternative for conventional COF test systems since it can fast and accurately detect variety of faults from fine pattern COF test process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.50-59
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• 2000

This paper presents a new SRAM testing method for various faults by monitoring dynamic power supply currents. The peak value of Iddt pulses when the transition write operation is performed, is prominently different from that of a fault free case. Using the observation, a new memory test algorithm is developed which consists of only write operations. The new test algorithm using dynamic power supply current testing, has length of 7n, where n is the number of cells in SRAMs. Compared to the previous March B algorithm, the test length has been reduced by 7/17, and can detect additional hard-to-detect faults.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.600-602
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• 1998

In this paper, we implement BIST to efficiently test circuits with pipeline architecture and JTAG to control implemented BIST and support board level test. Since implemented BIST is designed to be initialized using new seed, hard-to-detect faults are easily detected. Besides, to optimize area overhead, it uses JTAG instead of BIST controller and modified pipeline register instead of added test pattern generator and signature generator. And, to optimize pin overhead, it uses pins of JTAG. Function and efficiency of implemented BIST is verified by simulation.

• Journal of the Korea Institute of Military Science and Technology
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• v.20 no.5
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• pp.688-699
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• 2017

Model-based test, a well-known method of the black box tests, is consisted of the following four steps : model construction using requirement, test case generation from the model, execution of a SUT (software under test) and detection failures. Among models constructed in the first step, state-based models such as UML standard State Machine are commonly used to design event-based embedded systems (e.g., weapon control systems). To generate test cases from state-based models in the next step, coverage-based techniques such as state coverage and transition coverage are used. Round-trip path coverage technique using W-Method, one of coverage-based techniques, is known as more effective method than others. However it has a limitation of low failure observability because the W-Method technique terminates a testing process when arrivals meet states already visited and it is hard to decide the current state is completely same or not with the previous in the case like the GUI environment. In other words, there can exist unrevealed faults. Therefore, this study suggests a Extended W-Method. The Extended W-Method extends the round-trip path to a final state to improve failure observability. In this paper, we compare effectiveness and efficiency with requirement-item-based technique, W-Method and our Extended W-Method. The result shows that our technique can detect five and two more faults respectively and has the performance of 28 % and 42 % higher failure detection probability than the requirement-item-based and W-Method techniques, respectively.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.1
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• pp.43-62
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• 2017

Mobile pulse scanning Light Detection And Ranging (LIDAR) are essential components of intelligent vehicles capable of autonomous travel. Obstacle detection functions of autonomous vehicles require very low failure rates. With the increasing number of autonomous vehicles equipped with scanning LIDARs to detect and avoid obstacles and navigate safely through the environment, the probability of mutual interference becomes an important issue. The reception of foreign laser pulses can lead to problems such as ghost targets or a reduced signal-to-noise ratio. This paper will show the probability that any two scanning LIDARs will interfere mutually by considering spatial and temporal overlaps. We have conducted four experiments to investigate the occurrence of the mutual interference between scanning LIDARs. These four experimental results introduced the effects of mutual interference and indicated that the interference has spatial and temporal locality. It is hard to ignore consecutive mutual interference on the same line or the same angle because it is possible the real object not noise or error. It may make serious faults because the obstacle detection functions of autonomous vehicle rely on heavily the scanning LIDAR.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.26 no.6_spc
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• pp.714-720
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• 2016

Rubbing and misalignment are the most usual faults that occurs in rotating machinery and with them severe effect on power plant availability. Especially blade rubbing is hard to detect on FFT spectrum using the vibration signal. In this paper, the possibility of feature analysis of vibration signal is confirmed under blade rubbing and misalignment condition. And the lab-scale rotor test device provides the blade rubbing and shaft misalignment modes. Feature selection based on GA (genetic algorithm) is processed by the extracted feature of the time domain. Then, classification of the features is analyzed by using SVM (support vector machine) which is one of the machine learning algorithm. The results of features selection based on GA compared with those based on PCA (principal component analysis). According to the results, the possibility of feature analysis is confirmed. Therefore, blade rubbing and shaft misalignment can be diagnosed by feature of vibration signal.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.44-54
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• 2001

In this paper, a novel test method is proposed to detect the hard and soft fault in analog circuits. The proposed test method makes use of the offset voltage, which is one of the op-amps characteristics. During the test mode, CUT is modified to unit gain op-amps with feedback loop. When the input of the op-amp is grounded, a good circuit has a small offset voltage, but a faulty circuit has a large offset voltage. Faults in the op-amp which cause the offset voltage exceeding predefined range of tolerance can be detected. In the proposed method, no test vector is required to be applied. Therefore the test vector generation problem is eliminated and the test time and cost is reduced. In this note, the validity of the proposed test method has been verified through the example of the dual slope A/D converter. The HSPICE simulations results affirm that the presented method assures a high fault coverage.