• Journal of Institute of Control, Robotics and Systems
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• v.21 no.7
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• pp.669-676
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• 2015

In this paper, we described the simulation results of the phase offset performance of a clock in holdover mode which was normally operated in GPS Disciplined Oscillator (GPSDO). In the TIE model, we included the time error term caused by environmental temperature variation because one of the most important parameters of clock phase error is the frequency offset and drift caused by the variation of temperature. For the simulation, we employed Maximum Time Interval Error (MTIE) for the performance evaluation when the frequency offset and drift are estimated by using an Unbiased Finite Impulse Response (UFIR) filter with ladder algorithm. We assumed that the noise in the GPS measurement is white Gaussian with zero mean and 1 ns standard deviation, and temperature linearly varies with a slope of $1{^{\circ}C}$ per hour. From the simulation results, the followings were observed. First, with the estimation error of temperature of less than 3 % and the temperature compensation period of less than 900 seconds, the requirement of CDMA2000 phase synchronization under 10 us could be achieved for more than 40,000 seconds holdover time if we employ an OCXO (Oven Controlled Crystal Oscillator) clock. Second, in order to achieve the requirement of LTE-TDD under 1.5 us for more than 10,000 seconds holdover time, below 3 % estimation error and 500 seconds should be retained if a Rubidium clock is adopted.

• Journal of Positioning, Navigation, and Timing
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• v.5 no.3
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• pp.157-163
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• 2016

Clocks for time synchronization using radio signals such as global navigation satellite system (GNSS) may lose reference signals by intentional or unintentional jamming. This is called as holdover. When holdover occurs, a clock goes into free run in which synchronization performance is degraded considerably. In order to maintain the required precise time synchronization during holdover, accurate estimation on main parameters such as frequency offset and frequency drift is needed. It is necessary to implement an optimum filter through various simulation tests by creating clock noise in accordance with given specifications in order to estimate the main parameters accurately. In this paper, a method that creates clock noise in accordance with given specifications is described.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.107-110
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• 2005

This paper describes the design and fabrication of synchronous clock recovery module for S-DMB Gap Filler. Using the 2.304MHz TTL signal from gap filler tuner, clock recovery module with 10MHz output frequency including holdover function is designed. The measured performance of the clock recovery module shows a stability of less than 0.01ppm, 29 sec stability time, 10 sec holdover time, and maximum -113dBc/Hz@100Hz phase noise.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10A
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• pp.1003-1013
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• 2006

There is a serious problem in an 802.11g VoWLAN (Voice over Wireless LAN) terminal that talk time is less than 30% compared with an 802.11b terminal. It is almost impossible to achieve talk time level of the 802.11b MAC transmission method because IEEE 802.11g uses OFDM modulation, which is a kind of multi-carrier method and OFDM transmission speed is 54 Mbps faster than normal modulation. In this paper, a new concept of a Holdover time as a power saving method during a call with 802.11g terminal is suggested for the first time. Increase in the number of engaged terminals as a result of holdover time causes to QoS problem because of the increase in the number of back-off and then contention window. In this paper, to solve the QoS problem, a new approach is suggested such that when in down lint the sequence number of 802.11 G.711 is analyzed in the MAC of the terminal and then the Hold over time depending on loss rate is changed. Also, consumption of an electric current of 802.11b/g and MAC parameter's performance due to busy traffic caused by increase in the number of terminal are analyzed and then real data using VQT and Airopeek are analyzed.

• Journal of Positioning, Navigation, and Timing
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• v.13 no.1
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• pp.111-115
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• 2024

This study builds a machine learning model optimized for clocks among various techniques in the field of artificial intelligence and applies it to clock stabilization or synchronization technology based on atomic clock noise characteristics. In addition, the possibility of providing stable source clock data is confirmed through the characteristics of machine learning predicted values during holdover of atomic clocks. The proposed machine learning model is evaluated by comparing its performance with the AutoRegressive Integrated Moving Average (ARIMA) model, an existing statistical clock prediction model. From the results of the analysis, the prediction model proposed in this study (MSE: 9.47476) has a lower MSE value than the ARIMA model (MSE: 221.2622), which means that it provides more accurate predictions. The prediction accuracy is based on understanding the complex nature of data that changes over time and how well the model reflects this. The application of a machine learning prediction model can be seen as a way to overcome the limitations of the statistical-based ARIMA model in time series prediction and achieve improved prediction performance.

• Journal of Aerospace System Engineering
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• v.7 no.3
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• pp.51-57
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• 2013

This study describes the Federal Aviation Administration(FAA) certification policy for approving the use of Type II, III, and IV deicing/anti-icing fluids on small category airplanes. These fluids can be characterized as non-Newtonian, pseudo-plastic fluids, also known as "thickened" fluids. Deicing fluids are used before takeoff to remove frost or ice contamination, while anti-icing fluids are used before takeoff to prevent frost or ice contamination from occurring for a period of time(referred to as "holdover time") after application. Thickened deicing/anti-icing fluids can affect airplane performance and handling characteristics and their residue may cause stiff or frozen flight controls. This study also describes an approval process that may be used by type certificate holders and applicants for a type certificate under parts 23 to support operational use of these fluids on their airplanes.

• 한국ITS학회:학술대회논문집
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• v.2006 no.10
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• pp.108-112
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• 2006

• Journal of Communications and Networks
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• v.7 no.1
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• pp.1-12
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• 2005

Ethernet is being deployed in metropolitan area networks (MANs) as a lower-cost alternative to SONET-based infrastructures. MANs are usually required to support common communication services, such as voice and frame relay, based on legacy synchronous TDM technology in addition to asynchronous packet data transport. This paper addresses the clock synchronization problem that arises when transporting synchronous services over an asynchronous packet infrastructure, such as Ethernet. A novel algorithm for clock synchronization is presented combining time-stamp methods used in the network time protocol (NTP) with signal processing techniques applied to measured packet interarrival times. The algorithm achieves the frequency accuracy, stability, low drift, holdover performance, and rapid convergence required for viable emulation of TDM circuit services over Ethernet.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2019.11a
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• pp.77-80
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• 2019

GPS 항법 시스템은 재밍(jamming)에 취약한 것으로 알려져 있다. 실제로 2010년부터 북한은 서해상과 수도권에 GPS 전파교란 공격을 감행, 운행 중이던 선박과 항공기의 네비게이션 등에 다수의 장애현상을 유발시켰다. 이것에 대한 대안으로 eLoran(enhanced Long Range Navigation)이 GPS 항법 시스템을 보완할 수 있다고 알려져 있다. 이에 따라 해양수산부(MOF)는 기존 포항·광주 로란-C 송신국에 UTC(Coordinated Universal Time) 기반의 시각동기시스템 구축하여 지상파 eLoran 시스템으로 활용하기 위한 eLoran 사업을 진행하고 있다. 본 논문에서는 기존 포항·광주 로란-C 송신국에 UTC(Coordinated Universal Time) 기반의 시각동기시스템을 구축하기 위한 요구 사항을 살펴보고, 이 요구 사항에 따른 포항·광주 로란-C 시각동기시스템의 구축 결과에 대해 기술하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.423-429
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• 2007

The clock recovery module of gap filler for satellite DMB is proposed. Proposed module sustains the output frequency of 10 MHz whether the received signal from the satellite is unstable or cut off within 0.5 sec. The advantages of this module is without frequency tuning at regular interval and low material cost. This module is fabricated by using CPLD as clock recovery IC and new type of loop filter for satisfying the fast lock time and long hold over time simultaneously. The measured performance of the fabricated module has a holdover time of 11 sec at frequency stability less than 0.01 ppm, and phase noise of -113 dBc/Hz at 100 Hz offset.