• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2258-2263
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• 2006

In this parer, hump characteristics of short-channel nMOSFETs induced by moistures of the ILD(inter-layer dielectric) layer in the shallow trench isolation (STI) process are investigated and the method for hump suppression is proposed Using nMOSFETs with various types of the gate and a measurement of TDS-APIMS (Thermal Desorption System-Atmospheric Pressure ionization Mass Spectrometry), hump characteristics were systematically analyzed and the systemic analysis based hump model was presented; the ILD layer over poly-Si gate of nMOSFET generates moistures, but they can't diffuse out of the SiN layer due to the upper SiN layer. Consequently, they diffuses into the edge between the gate and STI and induces short-channel hump. In order to eliminate moisture in the ILD layer by out-gassing method, the annealing process prior to the deposition of the SiN layer was carried out. As the result, short-channel humps of the nMOSFETs were successfully suppressed.

• Transactions on Electrical and Electronic Materials
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• v.12 no.4
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• pp.131-134
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• 2011

Back-end-of-line using ultra low-k (ULK; k < 2.5) has been required to reduce resistive capacitance beyond 45 nmtechnologies, because micro-processing units need higher speed and density. There are two strategies to manufacture ULK inter-layer dielectric (ILD) materials using an air-gap (k = 1). The former ULK and calcinations of ILD degrade the mechanical strength and induce a high cost due to the complication of following process, such as chemical mechanical polishing and deposition of the barrier metal. In contrast, the air-gap based low-k ILD with a relatively higher density has been researched on the trench-type with activity, but it has limited application to high density devices due to its high air-gap into the next metal layer. The height of air-gap into the next metal layer was reduced by changing to the via-typed air-gap, up to about 50% compared to that of the trench-typed air-gap. The controllable ULK was easily fabricated using the via-typed air-gap. It is thought that the via-type air-gap made the better design margin like via-patterning in the area with the dense and narrow lines.

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.134-136
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• 2002

유리기판 위에서 제작된 다결정 실리콘 TFT(Thin Film Transistor) 에서는 열전도율이 낮은 실리콘 산화막 같은 물질이 사용되기 때문에 열에 대해서 낮은 임계점을 갖는다. 이로 인하여. 게이트와 드레인에 높은 전압이 걸리는 조건에서 동작시킬 경우에는 다결정 실리콘 TFT에서의 열화 현상이 두드러지게 나타나게 된다. 그러나, 열전도율이 실리콘 산화막(SiO2) 보다 열배 이상 높은 실리콘 질화막(SiNx)을 ILD(inter-layer dielectric) 재료로 사용했을 때 같은 스트레스 조건에서 다결정 실리콘의 신뢰성이 개선되는 것을 확인할 수 있었다.

• Journal of information and communication convergence engineering
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• v.14 no.1
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• pp.40-44
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• 2016

The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness T_ILD and dielectric constant ε_r of the inter-layer distance (ILD), the doping concentration N_d (N_a), and length L_g of the channel, and the side-wall length L_SW where the stacked FETs are coupled are studied. When N_d (N_a) < 10¹⁶ cm^-3 and L_SW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when N_d (N_a) > 10¹⁶ cm^-3 or L_SW > 20 nm, the shift decreases and increases, respectively. M3INVs with T_ILD ≥ 50 nm and ε_r ≤ 3.9 can neglect the interaction between the stacked FETs, but when T_ILD or ε_r do not meet the above conditions, the interaction must be taken into consideration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.173-174
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• 2018

This paper compared the electrical coupling of the monolithic 3D inverter consisting of MOSFET and JLFET. In the case of both the MOSFET and the JLFET, MOSFET and JLFET have a small threshold voltage variation when the thickness of inter-layer dielectric (ILD) = 100 nm. However, when the thickness of ILD = 10 nm, the threshold voltage variation is larger and the JLFET is twice as much as the MOSFET.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1121-1124
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• 2001

In this study, we verify th effects of pattern density on interlayer dielectric chemical mechanical polishing process based on the analysis of Preston's equation and confirm this analysis by several experiments. Appropriate modeling equation, transformed form Preston's equations used in glass polishing, will be suggested and described the effects of this modeling during pattern wafer ILD CMP. Results indicate that the modeling is well agreed to middle density structure of the die in pattern wafer, but has some error in low and high density structure of the die. Actually, the die used in Fab, was designed to have a appropriate density, therefore this modeling will be suitable for estimating the results of ILD CMP.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.812-816
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• 2000

It is very important to understand the correlation of between inter dielectric(ILD) CMP process and various facility factors supplied to equipment to equipment system. In this paper, the correlation between the various facility factors supplied to CMP equipment system and ILD-CMP process was studied. To prevent the partial over-polishing(edge hot-spot) generated in the wafer edge area during polishing, we analyze various facilities supplied at supply system. With facility shortage of D.I water(DIW) pressure, we introduced an adding purified $N_2$(P$N_2$)gas in polishing head cleaning station for increasing a cleaning effect. DIW pressure and P$N_2$gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. We estimated two factors (DIW pressure and P$N_2$gas) for the improvement of CMP process. Especially, we obtained a uniform planarity in patterned wafer and prohibited more than 90% wafer edge over-polishing. In this study, we acknowledged that facility factors supplied to equipment system played an important role in ILD-CMP process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.529-530
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• 2017

Electrical coupling of monolithic 3D inverter(M3D-INV) consisting of Junctionless FET(JLFET) was investigated. Depending on the thickness of Inter Layer Dielectirc (ILD) between top and bottom JLFETs, $N_{gate}-N_{gate}$ capacitance and transconductance $g_m$ are changed by the gate voltage of bottom JLFET. Therefore, when using a stacked structure with the ILD below tens nm, AC electrical coupling between two transistors in M3D-INV should be considered.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2899-2904
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• 2015

This paper introduces about the effect on $I_{DS}-V_{GS}$ characteristic of transistor that interface trap charge is created by damage due to heat in a 3D sequential inverter. A interface trap charge distribution in oxide layer in a 3D sequential inverter is extracted using two-dimensional device simulator. The variation of threshold voltage of top transistor according to the gate voltage variation of bottom transistor is also described in terms of Inter Layer Dielectric (ILD) length of 3D sequential inverter, considering the extracted interface trap charge distribution. The extracted interface trap density distribution shows that the bottom $HfO_2$ layer and both the bottom and top $SiO_2$ layer were relatively more affected by heat than the top $HfO_2$ layer with latest process. The threshold voltage variations of the shorter length of ILD in 3D sequential inverter under 50nm is higher than those over 50nm. The $V_{th}$ variation considering the interface trap charge distribution changes less than that excluding it.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.614-615
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• 2016

I studied electrical coupling of monolithic 3D inverter(M3D-INV) consisting of Junctionless FET(JLFET). If the thickness of Inter Layer Dielectric (ILD) between top JLFET and bottom JLFET is less than 50nm, current-voltage characteristic of top JLFET is rapidly changed by the gate voltage of bottom JLFET. Therefore, you have to consider about the electrical interaction according to the thickness between top JLFET and bottom JLFET in M3D-INV.