• The KIPS Transactions:PartC
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• v.9C no.5
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• pp.627-636
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• 2002

In this paper, we investigate the interworking method between three transport mechanisms, that is, ATM transport, IP$_v$4 transport and Ip$_v$6transport, where these mechanisms are wholly used in a Mobile RAN (Radio Access Network). The proposed interworking method, called Triple Capable Node, is to implement three transport mechanisms simultaneously in a single node so that the node can communicate directly to other nodes having various transport mechanisms by using one of three transport mechanisms. In addition, we propose a dynamic algorithm which selects one among multiple transport mechanisms at run time in order to achieve better communication performance.

• Proceedings of the Korea Multimedia Society Conference
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• 2001.06a
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• pp.265-269
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• 2001

멀티캐스트 라우팅 데몬은, 패킷 포워딩이 가능한 호스트 상에서 작동하여 호스트를 멀티캐스트 라우팅이 가능한 라우터로 만들어주는 역할을 하는 응용 프로그램이다. 현재의 리눅스 IP$_{v}$ 6 멀티캐스트 환경을 살펴보면 로컬 네트워트 상에서의 멀티캐스트 통신만을 지원하도록 되어있다. 즉 서로 다른 서브넷 상에 존재하는 호스트들 사이에서는 멀티캐스트 통신을 할 수 없다. 따라서, 본 논문에서는 리눅스 IP$_{v}$ 6 환경에서 멀티캐스트 라우팅이 가능하도록 IP$_{v}$ 6용 멀티캐스트 라우팅 데몬을 구현하였다. 멀티캐스트 라우팅이 가능하기 위해서는 두가지 문제가 해결되어야 하는데 첫째는 멀티캐스트 라우팅 정보를 주고받는 데몬 프로그램이고, 둘째는 데몬이 주고받은 라우팅 정보를 이용하여 멀티캐스트 패킷을 포워딩하는 커널 포워딩 루틴이다. 이 두가지가 본 논문에서 중심으로 다룰 내용이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2541-2547
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• 2010

In this paper, we propose a design technique which replaces logic transistors of 1.2V with medium-voltage transistors of 3.3V having small off-leakage current in repetitive block circuits where speed is not an issue, to implement a low-power eFuse OTP memory IP in the stand-by state. In addition, we use dual-port eFuse cells reducing operational current dissipation by reducing capacitances parasitic to RWL (Read word-line) and BL (Bit-line) in the read mode. Furthermore, we propose an equivalent circuit for simulating program power injected to an eFuse from a program voltage. The layout size of the designed 512-bit eFuse OTP memory IP with a 90nm CMOS image sensor process is $342{\mu}m{\times}236{\mu}m$. It is confirmed by measurement experiments on 42 samples with a program voltage of 5V that we get a good result having 97.6 percent of program yield. Also, the minimal operational supply voltage is measured well to be 0.9V.

• Proceedings of the Korea Society for Simulation Conference
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• 2005.11a
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• pp.3-7
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• 2005

The structure of $IP^2$(IP based-IMT Network Platform) as ubiquitous platform is three-layered model : Middleware including NCPF(Network Control Platform) and SSPF(Service Support Platform), IP-BB(IP-Backbone), Access network including Sensor network. A mobility management(MM) architecture in NCPF is proposed for $IP^2$. It manages routing information and location information separately. The existing method of multicast control in $IP^2$ is Remote Subscription. But Remote Subscription has problem that should be reconstructed whole Multicast tree when sender moves. To solve this problem, we propose a way to put Multicast Manager in NCPF.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.742-750
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• 2018

In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).

• The Journal of the Korea Contents Association
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• v.2 no.3
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• pp.119-126
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• 2002

The QoS(Quality of Service) guarantee mechanism is one of critical issues in the wireless network. Real-time applications like VoIP(Voice over IP) in All-IP networks need smooth handoffs in order to minimize or eliminate packet loss as a Mobile Host(MH) transitions between network links. In this paper, we design a new multicasting algorithm using DB(Dynamic Buffering) mechanism for Mobile-IPv6. A key feature of the new protocol is the concepts of the DB and MRA(Multicast Routing Agent) to reduce delivery path length of the multicast datagram. Particularly, the number of tunneling and average routing length of datagram are reduced relatively, the multicast traffic load is also decreased.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.144-151
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• 2022

In this paper, a 1.5V 256kb eFlash memory IP with low area DC-DC converter is designed for battery application. Therefore, in this paper, 5V NMOS precharging transistor is used instead of cross-coupled 5V NMOS transistor, which is a circuit that precharges the voltage of the pumping node to VIN voltage in the unit charge pump circuit for the design of a low-area DC-DC converter. A 5V cross-coupled PMOS transistor is used as a transistor that transfers the boosted voltage to the VOUT node. In addition, the gate node of the 5V NMOS precharging transistor is made to swing between VIN voltage and VIN+VDD voltage using a boost-clock generator. Furthermore, to swing the clock signal, which is one node of the pumping capacitor, to full VDD during a small ring oscillation period in the multi-stage charge pump circuit, a local inverter is added to each unit charge pump circuit. And when exiting from erase mode and program mode and staying at stand-by state, HV NMOS transistor is used to precharge to VDD voltage instead of using a circuit that precharges the boosted voltage to VDD voltage. Since the proposed circuit is applied to the DC-DC converter circuit, the layout area of the 256kb eFLASH memory IP is reduced by about 6.5% compared to the case of using the conventional DC-DC converter circuit.

• Journal of the Korean Chemical Society
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• v.41 no.3
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• pp.117-122
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• 1997

On the basis of our previous paper[Bull. Korean Chem. Soc. 1995, 16, 1015], the relative stability, ionization potential, and chemical reaction of the neutral and multiply charged $C_{60}$n ions(n=3+ to 6-) have been investigated by the semi-empirical MNDO method. $C_{60}^{1-}$ has the highest stability. The ionization potential values of the $C_{60}$ ions range from 15.31 eV of $C_{60}^{2+}$ to -13.01 eV of $C_{60}^{6-}$. These values show a linear relationship according to charges. The average IP per charge is 3.15 eV from our calculations and 3.22 eV from the linear function of IP. A charge- or electron-transfer reaction of $C_{60}^{n+}$ will only occur if the ionization potential of any guest molecule is lower than the electron affinity of the host $C_{60}^{n+}$. If the energy gap between ionization potential and electron affinity, ${\Delta}_{IP-EA}$, is high, charge-transfer reactions arise by the charge-controlled effect. However, if ${\Delta}_{IP-EA}$ is low, electron-transfer reactions arise by the frontier-controlled effect.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1002-1005
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• 2002

We have synthesized novel stilbenequinone derivatives(ASQ, PSQ) and investigated the properties of their electron drift mobility. Characteristics of the ionization potential Ip and electron affinity Ea of the ASQ were investigated by determining both oxidation and reduction potentials. There were estimated Ip = 7.1 eV and Ea = 3.6 eV. The electron drift mobility of ASQ mixture(R:t-Bu 10wt%) was $1.5{\times}10^{-5}cm^2/V{\cdot}sec$ at $6.15{\times}10^{5}V/cm$ and $1.3{\mu}m$ thickness.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.48-57
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• 2020

MCU used in applications such as wireless chargers and USB type-C require MTP memory with a small cell size and a small additional process mask. Conventional double poly EEPROM cells are small in size, but additional processing masks of about 3 to 5 sheets are required, and FN tunneling type single poly EEPROM cells have a large cell size. In this paper, a 110nm MTP cell using a vertical PIP capacitor is proposed. The erase operation of the proposed MTP cell uses FN tunneling between FG and EG, and the program operation uses CHEI injection method, which reduces the MTP cell size to 1.09㎛2 by sharing the PW of the MTP cell array. Meanwhile, MTP memory IP required for applications such as USB type-C needs to operate over a wide voltage range of 2.5V to 5.5V. However, the pumping current of the VPP charge pump is the lowest when the VCC voltage is the minimum 2.5V, while the ripple voltage is large when the VCC voltage is 5.5V. Therefore, in this paper, the VPP ripple voltage is reduced to within 0.19V through SPICE simulation because the pumping current is suppressed to 474.6㎂ even when VCC is increased by controlling the number of charge pumps turned on by using the VCC detector circuit.