• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2014년도 추계학술발표대회
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• pp.53-56
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• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.357-360
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• 2001

As SOC design methodology becomes popular, processors, the essential core in embedded system are required to be designed fast and supported to customers with expansive behavior description. This paper presents new methodology to meet such goals with designer configurable instruction set simulator for processors. This paper proposes new language called PML(Processor Modeling Language), which is based on microprogramming scheme and is also successful in most behavior of processors. By using this, we can describe scalar processor very efficiently with by-far faster simulation speed in compared with HDL model.

• 대한전자공학회논문지SD
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• 제45권10호
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• pp.53-58
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• 2008

본 논문은 네트워크 프로세서의 패킷 처리 능력 향상을 위한 새로운 명령어 세트를 제한한다. 제안하는 명령어는 패킷 헤더의 결합 연산을 가속화 할 수 있으므로 보다 효율적인 패킷 처리를 수행할 수 있다. 또한 overlay 명령어 처리를 위한 전용 하드웨어 구조를 설계하여 추가 하드웨어로 인한 비용을 최소화 하였다. 이를 위해 LISA 언어를 이용하여 네트워크 프로세서 기본 아키텍처를 설계하고 overlay 블록을 배럴 시프터를 기반으로 최적화 하였다. 이를 합성하여 면적 및 동작 지연시간을 비교하였으며, 컴파일러의 CKF(Compiler Known Function)를 이용하여 C레벨의 매크로 함수에 할당하고 어플리케이션 프로그램에 대한 실행 사이클 및 실행 시간을 비교하여 성능 향상을 확인하였다. Coware사의 processor designer, compiler designer를 이용하여 실험하였으며 Synopsys의 TSMC $0.25{\mu}m$로 합성한 결과 20.7%의 동작 지연시간 감소를 보였고, 전체 실행 사이클에선 제안하는 명령어 세트에 의해 30.8%의 성능 향상을 보였다.

• 전자공학회논문지CI
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• 제45권3호
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• pp.142-148
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• 2008

복호된 영상의 블록 경계에서 발생하는 왜곡을 보정하기 위해 사용된 H.264/AVC 표준의 디블록킹 필터는 개선된 품질의 영상을 제공하지만, 이에 사용되는 복잡한 필터링 연산은 복호기의 처리 시간을 지연시키는 주된 요인이 되고 있다. 본 논문에서는 이러한 필터링 연산을 더 빠르게 수행할 수 있는 명령어를 제안하고 ASIP을 구성하여 디블록킹 필터를 가속하였다. LISA를 이용하여 MIPS 기반의 기준 프로세서를 설계하고 디블록킹 필터 모델을 시뮬레이션하여 제안하는 명령어 적용에 따른 실행 사이클의 성능 향상을 비교하였으며, 설계된 기준 프로세서를 CoWare의 Processor Designer를 통해 HDL을 생성하고 Synopsys의 Design Compiler를 이용하여 TSMC 0.25um 공정으로 합성하고 제안하는 명령어를 추가할 경우에 대해 면적 및 동작 지연시간 등을 비교하였다. 합성 결과, 제안하는 명령어 셋을 적용함에 따라 면적 및 동작 지연시간에서 각각 7.5%와 3.2%의 증가를 보였으며, 이로 인해 실행 사이클 면에서는 평균 18.18%의 성능 향상을 보였다.

• 전자공학회논문지B
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• 제32B권1호
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• pp.21-29
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• 1995

In this paper, a independent and structured microassembler was designed for easily changing the system design, and for designing various microarchitecture. When the designer's hardware and microprogramming process were made concurrently, it is needed to easily change or improve the instruction set and executable code format. But this type of developed environment requires a high const and a large software system. A proposed microassembler was designed so the designer directly defines the microinstruction set and format to be executed. And we implemented a module from each part of the software, so it is now possible to use practically and upgrade the function of each part, First, the symbol was separated from the assembler. And then microinstruction was copied into it. The microinstruction format was designed using the defined language that was designed for free microinstruction. This was implemented in an IBM-PC by using the C-language, FLEX,and BISON.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
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• pp.848-851
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• 1997

A graphic simulation program is developed to assimilate the remote dismantling process of research nuclear reactors. This program makes extensive use of a commercial robot graphic instruction program. Firstly, a realistic graphic model of research reactors are built along with various dismantling equipments. Using the graphic instruction languages provided by IGRIP, then, a graphic process simulation program is developed that operates interactively with the user. Consequently, it is made possible for a process designer to visualize an arbitrary dismantling sequence and interactively modify the process. It is expected that the developed system will be utilized as an effective operator aid in both design and execution phases of remote dismantling of research reactor.

• 대한전자공학회논문지SD
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• 제48권12호
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• pp.58-65
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• 2011

본 논문은 H.264/AVC, MPEG4 등, 다양한 영상압축 코덱을 지원할 수 있는 ME ASIP (Application-specific Instruction Processor)의 정화소 움직임 추정 전용 명령어와 재구성 가능한 하드웨어 구조를 제안한다. 제안하는 전용의 명령어와 하드웨어 가속기는 HD급의 고화질 영상을 지원할 수 있는 성능을 가지고 있다. 제안하는 정화소 움직임 추정 명령어는 다수의 병렬 연산과 패턴 정보를 이용한 가변 포인트 2D SAD 연산기 구조를 통하여 전역탐색을 비롯한 각종 고속 탐색 알고리즘을 지원한다. 이를 위한 하드웨어 구조는 128개의 Processor Elements (PEs)로 구성되어 있는 Processor Element Group (PEG) 하나당 25,500 게이트를 가진다. 제안하는 ASIP은 Synopsys 사의 Processor Designer 로 검증하였고, Design Compiler를 이용 IBM 90nm 공정으로 합성하였다. 그 결과 제안하는 ASIP의 하드웨어 사이즈는 453K 게이트였으며, 동작 주파수는 188MHz로 HD급 1080p의 해상도를 가지는 영상을 실시간으로 동작 시킬 수 있다. 본 논문은 기존 2D SAD ASIP에 비하여 하드웨어 사이즈 측면에서 26%, 연산 속도 측면에서 평균 18%의 성능 향상을 보인다.

• 한국통신학회논문지
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• 제15권1호
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• pp.29-42
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• 1990

본 논문에서는 16-비트의 소형명령의 프로세서를 설계할 때 IDL로서의 APL를 사용하고 있다. 그것은 다른 HDL들이 갖지못하는 하드웨어의 구조를 표현하고 기술하는 것이 가능했다. 여기서는 프로세서를 설계할때 전체적인 시스템을 모듈별로 분리하여 설계하였기 때문에, 직접 코딩 방법을 선택하였다. 설계된 각 모듈들은 실험체제를 통하여 입력된 12-비트의 제어워드에 따라 실행되며, 그 실험체제는 기호화된 명령어들로 구성된다. 여기서, 2진코드를 사용하여 SIP의 명령코드를 세팅함으로써, 명령형식과 어셈블러 명령을 구성했고, 실험체제를 통하여 제시된 명령어 세트를 입력함으로써 SIP의 동작을 확인했다. 제시된 SIP에서는 입력하는 프로그램이 기호화된 언어이기 때문에 설계자나 사용자가 시스템의 동작을 쉽게 이해할 수 있을 것이다. 특히, SIP내에서 유니트함수를 임의로 정의할 수 있기 때문에 유니트함수의 사용에 제한을 받지않고 다양하고 쉽게 호출할 수 있을 것이다.

• 한국응급구조학회지
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• 제23권1호
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• pp.19-33
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• 2019

Purpose: The aim of this study was to provide basic data to aid in the effective adoption of the preceptor system for new paramedics by assessing the preceptor role awareness among senior 119 paramedics in the field. Methods: A questionnaire was administered to 182 senior paramedics who each had more than 3 years field experience. The questionnaire measuring preceptor role awareness was composed of 64 items with responses based on a 5 point Likert scale. Data were collected from July 31, 2018 to August 29, 2018, and were analyzed with IBM SPSS version 24.0. Results: The average score for preceptor role awareness was 3.87 (supervisor = 3.95, resource person = 3.88, role model = 3.85, and instruction designer = 3.81). There were significant differences in preceptor role awareness among the participants based on competence (p =.002) and clinical skill (p =.000). Also, there were high positive correlations between preceptor role awareness and its subdivision (p <.01). Conclusion: For effective operation of the preceptor system in the future, the preceptors' role as designers of instruction and role models should be enhanced, Also, future preceptors are very important in the improvement of competence and clinical skill in the preceptor system. Therefore, it is necessary to provide training that enables new preceptors to effectively adopt and operate the preceptor system.

• 유통과학연구
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• 제16권7호
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• pp.67-75
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• 2018

Purpose - In the 21st century, as information technology advances alongside the emergence of the 4th generation, industrial age, industrial environment has become individualized and customized. It is important to hire good quality employees for good service in the industry. The e-learning market is growing every year. Although e-learning companies are finding better quality employees in e-learning, it is not easy to find it. Companies also spend a lot of time and cost to find employee. On the employees side, they want to get a job freely when they want, but they cannot find their job easily. Furthermore, the labor market environment is changing fast. In the 4th generation, industrial age, employers require to find manpower whenever they need and want at little cost. So of their own accord, we have considered the necessity of management of human resources for employees and employers in e-learning. The purpose of this study is to propose a human cloud platform framework for enabling an efficient management of human resources in e-learning industry. Research design, data, and methodology - To pinpoint the items of a human cloud platform framework, the study was initiated according to the following process. First, items of competency relating to e-learning instructional designer was analyzed. Second, based on the items of information from this analysis, selection and validity verification took place with 5 e-learning specialists group. Third, the opinion of experts who were in charge of hiring in e-learning companies were collated with the questionnaire. Lastly, the human cloud platform framework was proposed based on opinion results. Results - The framework was comprised of 7 domains and 27 items in order to develop the human cloud platform for e-learning instructional designer. The analysis results showed that the most highly considered item were 'skill (4.60)' that employee already have the capability. Following this (in order) were 'project type (4.56)', 'work competency (4.56)', and 'strength area of instructional design (4.52)'. Conclusions - The 27 items in the human cloud platform framework were suggested in this study. Following this, we can consider to develop the human cloud platform for finding a job and hiring e-learning instructional designer easily. For successful platform operation, we need to consider reliability between employer and employee. In addition, we need quality assurance system based on operation has public confidence.