• The KIPS Transactions:PartB
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• v.12B no.2 s.98
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• pp.131-136
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• 2005

Motion Estimation (ME) has been developed to remove redundant data contained in a sequence of image. And ME is an important part of video encoding systems, since it can significantly affect the qualify of an encoded sequences. Generally, ME consists of two stages, the integer pixel motion estimation and the half pixel motion estimation. Many methods have been developed to reduce the computational complexity at the integer pixel motion estimation. However, the studies are needed at the half pixel motion estimation to reduce the complexity. In this paper, a method based on the correlations between integer pixel motion vectors and half pixel motion vectors is proposed for the half pixel motion estimation. The proposed method has less computational complexity than the full half pixel search method (FHSM) that needs the bilinear interpolation of half pixels and examines nine half pixel points to the find the half pixel motion vector. Experimental results show that the speedup improvement of the proposed method over FHSM can be up to $2.5\~80$ times faster and the image quality degradation is about to $0.07\~0.69(dB)$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10C
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• pp.948-955
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• 2006

In this paper, we propose motion estimation and compensation using Low-Band-Shift(LBS) with Integer Lifting Shift property. To overcome shift-variant property on wavelet coefficients, the LBS was previously proposed. This method which is applied to reference frame in video coding technique has superior performance in terms of rate-distortion characteristic. However, this method needs more memory and computational complexity. For the enhancement of those disadvantages, we propose motion estimation using Low-Band-Shift with Integer Lifting. The Integer Lifting implementation gives us good efficiency of calculation and storage.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.639-642
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• 2005

Motion Estimation(ME) is an important part of video compression, because it requires a large amount of computation. Half-pixel and quarter-pixel motion estimation allows high video compression rates but it also has high computation complexity. In this paper we suggest a new and efficient motion estimation algorithm for half-pixel and quarter-pixel motion estimation using SAD values. In the method, an integer-pixel motion vector is found and then only three neighboring points of the integer-pixel motion vector is evaluated to find the half-pixel motion vector. The quarter-pixel motion vector is also found by using a similar method. Experimental results of our method shows 20% reduction in computation time, when compared with those of a conventional method, while producing same quality motion vectors.

• Journal of Korea Multimedia Society
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• v.21 no.1
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• pp.18-25
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• 2018

In High Efficiency Video Coding (HEVC), integer motion estimation (IME) requires a large amount of computational complexity because HEVC adopts the high flexible and hierarchical coding structures. In order to reduce the computational complexity of IME, this paper proposes the search range reduction algorithm, which takes advantage of motion vectors similarity between different layers. It needs only a few modification for HEVC reference software. Based on the experimental results, the proposed algorithm reduces the processing time of IME by 28.1% on average, whereas its the $Bj{\emptyset}ntegaard$ delta bitrate (BD-BR) increase is 0.15% which is negligible.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.388-396
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• 2003

In this paper, a fast motion search algorithm that performs motion search for variable blocks in integer pixel unit is proposed. The proposed method is based on the successive elimination algorithm (SEA) using sum norms to find the best estimate of motion vector and obtains the best estimate of the motion vectors of blocks, including 16${\times}$8, 8${\times}$16, and 8${\times}$8, by searching eight pixels around the best motion vector of 16${\times}$16 block obtained from all candidates. And the motion vectors of blocks, including 8${\times}$4, 4${\times}$8, and 4${\times}$4, is obtained by searching eight pixels around the best motion vector of 8${\times}$8 block. The proposed motion search is applied to the H.264 encoder that performs variable blocks motion estimation (ME). In terms of computational complexity, the proposed search algorithm for motion estimation (ME) calculates motion vectors in about 23.8 times speed compared with the spiral full search without early termination and 4.6 times speed compared with the motion estimation method using hierarchical sum of absolute difference (SAD) of 4${\times}$4 blocks, while it shows 0.1dB∼0.4dB peak signal-to-noise ratio (PSNR) drop in comparison to the spiral full search.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.397-403
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• 2014

A new video compression standard called High Efficiency Video Coding (HEVC) has recently been released onto the market. HEVC provides higher coding performance compared to previous standards, but at the cost of a significant increase in encoding complexity, particularly in motion estimation (ME). At the same time, the computing capabilities of Graphics Processing Units (GPUs) have become more powerful. This paper proposes a parallel integer-pel ME (IME) algorithm for HEVC on GPU using the Compute Unified Device Architecture (CUDA). In the proposed IME, concurrent parallel reduction (CPR) is introduced. CPR performs several parallel reduction (PR) operations concurrently to solve two problems in conventional PR; low thread utilization and high thread synchronization latency. The proposed encoder reduces the portion of IME in the encoder to almost zero with a 2.3% increase in bitrate. In terms of IME, the proposed IME is up to 172.6 times faster than the IME in the HEVC reference model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.28-34
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• 2011

In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The H.264/AVC motion estimation chip is fabricated on a MPW(Multi-Project Wafer) chip using the chartered $0.18{\mu}m$ standard CMOS 1P5M technology and achieves high throughput supporting HDTV 720p 30 fps.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.321-325
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• 2009

Sub-pel level motion estimation contributes to significant increase in R-D performance for H.264|MPEG 4 Part 10 AVC. However, several supplements, such as interpolation, block matching, and Hadamard transform which entails large computational complexity of encoding process, are essential to find best matching block in sub-pel level motion estimation and compensation. In this paper, a fast motion estimation scheme in sub-pel accuracy is proposed based on a parabolic model of SAD to avoid such computational complexity. In the proposed scheme, motion estimation (ME) is only performed in integer-pel levels and the following sub-pel level motion vectors are found from the parametric SAD model for which the model parameters are estimated from the SAD values obtained in the integer-pel levels. Fall-back check is performed to ensure the validity of the parabolic SAD model with the estimated parameters. The experiment result shows that the proposed scheme can reduce the motion estimation time up to about 30% of the total ME times in average with negligible amount of PSNR drops (0.14dB in maximum) and bit increments (2.54%in maximum).

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.430-442
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• 2013

This paper presents a fast multi-reference frame integer motion estimator for H.264/AVC. The proposed system uses the previously proposed fast multi-reference frame algorithm. The previously proposed algorithm executes a full search area motion estimation in reference frames 0 and 1. After that, the search areas of motion estimation in reference frames 2, 3 and 4 are minimized by a linear relationship between the motion vector and the distances from the current frame to the reference frames. For hardware implementation, the modified algorithm optimizes the search area, reduces the overlapping search area and modifies a division equation. Because the search area is reduced, the amount of computation is reduced by 58.7%. In experimental results, the modified algorithm shows an increase of bit-rate in 0.36% when compared with the five reference frame standard. The pipeline structure and the memory controller are also adopted for real-time video encoding. The proposed system is implemented using 0.13 um CMOS technology, and the gate count is 1089K with 6.50 KB of internal SRAM. It can encode a Full HD video ($1920{\times}1080P@30Hz$) in real-time at a 135 MHz clock speed with 5 reference frames.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.383-384
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• 2007

In this paper, we propose the new and simple method for sub-pixel block search algorithm by only using integer-pixel for motion estimation and compensation. In many papers, the fast search block match algorithms based on TSS have been proposed. However, these methods could be achieved a little reduction of the computational complexity. All of searching points by 1/4-pixel have own predicted integer-pixel SAD array. Therefor, if we know initial nine SAD values by integer, which is on the searching area of the reference frame, then we can find optimal searching point by 1/4-pixel, directly.