• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.2
• /
• pp.47-54
• /
• 2004

Up to the present, there have been many works to analyze interconnects on timing aspects, while less works have been done on power aspects. As resistance of interconnects and rise time of signals increase, power consumption associated with interconnects is ever-increasing. In case of clock trees, particularly power consumption associated with interconnects is over 30％ of total power consumption. Hence, an efficient method to compute power consumption of interconnects is necessary and in this paper we propose a simple yet accurate method to estimate dynamic power consumption of interconnects. We propose a new reduced-order model to estimate power consumption of large interconnects. Through the proposed model which is directly derived from total capacitance and resistance of interconnects, we show that the dynamic power consumption of whole interconnects can be approximated, and propose an analytical method to compute the power consumption. The results applying the proposed method to various RC networks show that average relative error is 1.86％ and maximum relative error is 9.82％ in comparison with HSPICE results.

• Journal of the Korean Ceramic Society
• /
• v.51 no.4
• /
• pp.231-242
• /
• 2014

An interconnect in solid oxide fuel cells (SOFCs) electrically connects unit cells and separates fuel from oxidant in the adjoining cells. The interconnects can be divided broadly into two categories - ceramic and metallic interconnects. A thin and gastight ceramic layer is deposited onto a porous support, and metallic interconnects are coated with conductive ceramics to improve their surface stability. This paper provides a short review on ceramic materials for SOFC interconnects. After a brief discussion of the key requirements for interconnects, the article describes basic aspects of chromites and titanates with a perovskite structure for ceramic interconnects, followed by the introduction of dual-layer interconnects. Then, the paper presents protective coatings based on spinel-or perovskite-type oxides on metallic interconnects, which are capable of mitigating oxide scale growth and inhibiting Cr evaporation.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.54 no.8
• /
• pp.350-354
• /
• 2005

This paper proposes a new method for delay time calculation in RLC interconnects. This method is simple, but precise. The proposed method can calculate delay time of RLC interconnects by simple numerical formula calculation without complex moment calculation using reduced model in RLC interconnects. The results using the proposed method for RLC circuits show that average relative error is within $10\%$ in comparison with HSPICE simulation results.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.3
• /
• pp.73-84
• /
• 2002

Fast and accurate new capacitance determination methodology for non-uniform complicated multi-layer VLSI interconnects is presented. Since a capacitance determination of intricate multi-layer interconnects using 3-dimensional field-solver is not practical, quasi-3-dimensional methodology is presented. Interconnects with discontinuity (i.e., bend structure and different spacing between lines, etc.) are partitioned. Then, each partial capacitance of divided parts is extracted by using 2-dimensional extraction methodology. For a multi-layer interconnects with shielding layer, the system can be simplified by investigating a distribution of charge in it. Thereby, quasi-3-dimensional capacitance for multi-layer interconnects can be determined by combining solid-ground based 2-dimensional capacitance and shielding effect which is independently determined with layout dimensions. This methodology for complicated multi-layer interconnects is more accurate and cost-efficient than conventional 3-dimensional methodology It is shown that the quasi-3-dimensional capacitance methodology has excellent agreement with 3-dimensional field- solver-based results within 5% error.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.7
• /
• pp.20-29
• /
• 1998

As the packing density of ICs in recent submicron IC design increases, interconnects gain importance. Because interconnects directly affect on two major components of circuit performance, power dissipation and operating speed, circuit engineers are concerned with the optimal design of interconnects and the aid tool to design them. When circuit models of interconnects are given (including geometry and material information), the analysis process for the given structure is not an easy task, but conversely, it is much more difficult to design an interconnect structure with given circuit characteristics. This paper focuses on the latter process that has not been foucsed on much till now due to the complexity of the problem, and prsents a design aid tool(DATOIS) to synthesize interconnects. this tool stroes the circuit performance parameters for normalized interconnect geometries, and has two oeprational modes:analysis mode and synthesis mode. In the analysis mode, circuit performance parameters are obtained by searching the internal database for a given geometry and interpolates results if necessary . In thesynthesis mode, when a given circuit performance parameter satisfies a set of geometry condition in the database, those geometry structures are printed out.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.5
• /
• pp.13-26
• /
• 1999

This paper presents a metric that can guide to optimal circuit models for interconnects among various models, given interconnect parameters and operating environment. To get this goal, we categorize interconnects into RC~c1ass and RLC-c1ass model domains based on the quantitative modeling error analysis using total resistance, inductance and capacitance of interconnects as well as operating frequency. RC~c1ass circuit models, which include most on~chip interconnects, can be efficiently analyzed by using the model~order reduction techniques. RLC-c1ass circuit models are constructed using one of three candidates, ILC(Iterative Ladder Circuit) macromodels, MC(Method of Characteristics) macromodels, and state-based convolution method, the selection process of which is based upon the allowable modeling error and electrical parameters of interconnects. We propose the model domain diagram leading to optimal circuit models and the division of model domains has been achieved considering the simulation cost of macromodels under the environmental assumption of the general purpose circuit simulator such as SPICE. The macromodeling method presented in this paper keeps the passivity of the original interconnects and accordingly guarantees the unconditional stability of circuit models.

• Journal of the Microelectronics and Packaging Society
• /
• v.22 no.1
• /
• pp.21-25
• /
• 2015

Bending fatigue characteristics of Cu films and $8{\mu}m$ width Cu interconnects on flexible substrates were investigated, and fatigue reliability improvement was achieved through Mo-Ti alloy adhesion layer. Tensile bending fatigue reliability of Cu interconnects is 3 times lower than that of Cu films, and even compressive bending fatigue reliability of Cu interconnects is 6 times lower than that of Cu films. From these results, mechanical crack formation could be fatal in Cu interconnects. With Mo-Ti adhesion layer, fatigue reliability of Cu films and interconnects were enhanced due to the increase of adhesion strength and the suppression of slip induced crack initiation.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.70-73
• /
• 2002

High frequency digital LSI circuits are usually composed of many sub-circuits coupled with interconnects. They sometimes causes serious problems of the fault switching by time-delays, crosstalks, reflections of signals and so on. Therefore, it is very important to develop a user-friendly simulator for solving these problems. Although a moment matching method is widely used as the reduction technique of interconnects, it may happen to arise erroneous results for evaluating the poles far from the origin. In this paper, we show an asymptotic method in the complex frequency-domain, where we calculate the exact poles and residues giving large effect to the transient responses. Then, the interconnects are replaced by the asymptotic equivalent circuits using the poles and residues. Thus, we can develop a users-friendly simulator using the equivalent circuits.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.8
• /
• pp.1547-1554
• /
• 2011

As process parameters scale, interconnect width are reduced rapidly while the current flowing through interconnects does not decrease in a proportional manner. This effect increases current density in metal interconnects which may result in poor reliability. Since RMS(root-mean-square) current limits are used to evaluate self-heating and short-time stress failures caused by high-current pluses, RMS current estimation is very important to guarantee the reliability of semiconductor systems. Hence, it is critical to estimate the current limits through interconnects earlier in semiconductor design stages. The purpose of this paper is to propose a fast, yet accurate RMS current estimation technique that can offer a relatively precise estimate by using closed-form equations. The efficiency and accuracy of the proposed method have been verified through simulations using HSPICE for a vast range of interconnect parameters.

• Journal of Electrical Engineering and Technology
• /
• v.6 no.2
• /
• pp.280-283
• /
• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.