• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.34-44
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• 2006

A system-on-a-chip (SoC) design uses pre-verified IP hardware blocks in order to reduce design time. We need interface circuits to connect IPs with different protocols. In SoC design we should design interface circuits frequently and these tasks are somewhat time-consuming and error-prone. So it is necessary to generate the interface circuits automatically. Several studies have been made on generating interface circuits only from the communication protocols of IPs. With existing approaches, it is not easy to generate interface circuits connecting two IPs only from communication protocols: connection between IP with address and W without address, connection between IP with only one port to transfer address/data and IP with different ports for address and data connection between IP that transfer address and data together and IP that transfer only one address with a number of data in a burst. No consideration of various characteristics of IPs and no changed algorithm are responsible for it. In order to solve this problem, the proposed approach categorizes communication protocols of IPs, and takes characteristics matching of IPs into account during the interface synthesis. In experiments, we show that we could correctly generate and verify interface circuits for IPs with different characteristics.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.2
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• pp.84-89
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• 2013

In this paper, we propose interface circuits for reducing power consumption and EMI when sequences of data from LCD controller to LCD driver IC by transmitting two bit data during one clock period. The proposed circuits are operated in current mode, which is different from conventional voltage-mode signaling techniques, and also employ threshold technique of Modified-LVDS(Low Voltage Differential Signaling) method. We have simulated the proposed circuits using H-SPICE tool for performance analysis of the proposed method. The simulation results show that the proposed circuits provide a faster transmission speed and stronger noise immunity than the conventional LVDS circuits. It might be suitable for the real-time transmission of huge image data in LCD system.

• Journal of Power Electronics
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• v.11 no.1
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• pp.1-9
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• 2011

This paper describes a two quadrant bidirectional soft switching converter for ultra capacitor interface circuits. The total efficiency of the energy storage system in terms of size and cost can be increased by a combination of batteries and ultra capacitors. The required system energy is provided by a battery, while an ultra capacitor is used at high load power pulses. The ultra capacitor voltage changes during charge and discharge modes, therefore an interface circuit is required between the ultra capacitor and the battery. This interface circuit must have good efficiency while providing bidirectional power conversion to capture energy from regenerative braking, downhill driving and the protecting ultra capacitor from immediate discharge. In this paper a fully soft switched two quadrant bidirectional soft switching converter for ultra capacitor interface circuits is introduced and the elements of the converter are reduced considerably. In this paper, zero voltage transient (ZVT) and zero current transient (ZCT) techniques are applied to increase efficiency. The proposed converter acts as a ZCT Buck to charge the ultra capacitor. On the other hand, it acts as a ZVT Boost to discharge the ultra capacitor. A laboratory prototype converter is designed and realized for hybrid vehicle applications. The experimental results presented confirm the theoretical and simulation results.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.929-932
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• 1993

A fuzzy microcontroller is presented implementing a simplified inference mechanism. Fuzzification, rule composition and defuzzification are carried out by means of (basically) analog current-mode CMOS circuits operating in strong inversion. Also a voltage interface is provided with the external world. Combining analog and digital techniques allow a programming capability.

• Journal of Communications and Networks
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• v.1 no.3
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• pp.201-212
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• 1999

This paper studies the rapid design and implementation of the medium access control(MAC) and related interface circuits for 802.11 wireless LANs based on the field programmed gate ar-ray(FPGA) technology. Our design is thus aimed to support both the distributed coordination function (DCF) and the point coordination function(PCF) with the aid of FPGA technology. Further-more, in an infrastructure network, some stations may serve as the access points (APs) which may function like a learning bridge. This paper will also discuss how to design for such application. The hardware of the MAC and interface may at least consist of three major parts: wireless transmission and reception processes and in-terface, host(bus) interface, and the interface to the distributed system (optional). Through the increasing popularity of FPGA de-sign, this paper presents how Complex Programmable Logic De-vices(CPLD) can be utilized for speedy design of prototypes. It also demonstrates that there is much room for low-cost hardware prototype design to accelerate the processing speed of the MAC control function and for field testing.

• Progress in Superconductivity
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• v.5 no.1
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• pp.55-60
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• 2003

We designed and constructed integrated 3-channel flux-locked-loop (FLL) electronic system for the control and readout of high-T$_{c}$ SQUIDs. This system consists of low noise preamplifiers, integrators, interface circuits, and software. FLL operation was carried out with biased signals of 19 KHz modulated current and 150 KHz modulated flux, which are reconstructed as detected signals by preamplifier and demodulator. Computer controlled interface circuits regulate FLL circuit and adjust SQUID parameters to the optimum operating condition. The software regulates interface circuits to make an auto-tuning for the control of SQUIDs, and displays readout data from FLL circuit. 3-channel SQUID electronic system was assembled with 3 FLL-interface circuit boards and a power supply board in the aluminum case of 56 mm ${\times}$ 53 mm${\times}$ 150 mm. Overall noise of the system was around 150 fT/(equation omitted)Hz when measured in the shielded room, 200 fT/(equation omitted)Hz in a weakly shielded room, respectively.y.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2609-2612
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• 2003

This paper describes a 64 channel signal generator/analyzer module that is useful for verification and testing of digital circuits. It can perform logic analyzer function and signal generator function at the same time. The 64 Channel module is implemented with single FPGA chip for miniaturization, and an USB interface is used to increase portability of the module. Multiple modules can be used in parallel for the verification of large scale circuits. Moreover, since the module is implemented as a PC based system, one can configure convenient GUI(Graphic User Interface) environment.

• Electrical & Electronic Materials
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• v.8 no.3
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• pp.254-260
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• 1995

A method is described for the design and fabrication of the sensor interface circuits on the Clark electrodes for the dissolved oxygen(DO). The discussion includes a method for the +5 V single-supply driving for the sensor circuits, which has low power comsumption for the front-end electronics. DO probe under test is composed of the Clark electrode with silver anode, gold cathode and the electrolyte of half saturated KCI solution and the FEP teflon memtrance for the oxygen penetration. Typical polarograms for the DO probes by using this sensor circuit reveals high accuracy over 99% of the I to V conversion. Partial pressure of oxygen obtained from the polarograms are well suited to the results calculated. It is expected that the proposed sensor circuits can be utilized into the customized IC for the battery-driven small-size DO meters.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.674-676
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• 2008

An electrostatic discharge (ESD) or a noise supplied from the outside has an effect on communication between the timing controller (TCON) and the memory element (EEPROM) through the interface between the timing controller and the memory element in liquid crystal displays (LCD). Therefore, we must apply ESD protection methods to LCD operating circuits for a normal operation. Our ESD protection circuit is to prevent from bi-directional communication errors between TCON and EEPROM due to an electrostatic discharge (ESD).

• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.