• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.514-523
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• 2006

In this paper we propose an extended interleaving technique to improve a detailed placement. The existing row-based interleaving technique allows cells to move only within a row and it can be applied when there is no space between cells. The proposed extended-interleaving technique releases such constraints so that cells can move along with a vertical line parallel to a y-axis and space between cells is properly handled. Converged detailed-placements by a mature CAD tool have been improved by the proposed interleaving technique by 9.5% on average in half-perimeter wire length.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.445-454
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• 2015

As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1515-1526
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• 2019

Ear-piercing high-frequency noise from electromagnetic vibrations in motors has become unacceptable in sensitive environments, due to the application of pulse width modulation (PWM) and in consideration of switching losses. This paper proposed a synchronous periodic frequency modulation (SPFM) method based on the interleaving technique for paralleled three-phase voltage source inverters (VSIs) to eliminate PWM vibration noise. The proposed SPFM technique is able to effectively remove unpleasant high-frequency vibration noise as well as acoustic noise more effectively than the conventional periodic carrier frequency modulation (PCFM) and interleaving technique. It completely eliminates the vibration noise near odd-order carrier frequencies and reduces the PWM vibration noise near even-order carrier frequencies depending on the switching frequency variation range. Furthermore, the SPFM method is simple to implement and does not employ additional circuits in the drive system. Finally, the effectiveness of the proposed method has been confirmed by detailed experimental results.

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.1983-1988
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• 2015

This paper proposes the enhanced application of superconducting magnetic energy storage (SMES) for the effective compensation of power fluctuations based on the interleaving technique. With increases in demand for renewable energy based photovoltaic (PV) generation system, the output power fluctuations from PV generation system due to sudden changes in environmental conditions can cause serious problems such as grid voltage and frequency variations. To solve this problem, the SMES system is applied with its superior characteristics with respect to high power density, fast response for charge and discharge operations, system efficiency, etc. In particular, the compensation capability is effectively improved by the proposed interleaving technique based on its parallel structure. The dynamic performance of the system designed using the proposed method is evaluated with several case studies through time-domain simulations.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.4
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• pp.443-448
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• 2014

Soft errors in memory devices that caused by radiation are the main threat from a reliability point of view. This threat can be commonly overcome with the combination of SEC (Single-Error Correction) codes and scrubbing technique. The interleaving architecture can give memory devices the ability of tolerating these soft errors, especially against multiple-bit soft errors. And the interleaving distance plays a key role in building the tolerance against multiple-bit soft errors. This paper proposes a reliability model of an interleaved memory device which suffers from multiple-bit soft errors and are protected by a combination of SEC code and scrubbing. The proposed model shows how the interleaving distance works to improve the reliability and can be used to make a decision in determining optimal scrubbing technique to meet the demands in reliability.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3290-3299
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• 2000

Digital watermarking has similar concepts with channel coding thechnique for transferring data with minimizing error in noise environment, since it should be robust to various kinds of data manipulation for protecting copyrights of multimedia data. This paper proposes a digital watermarking technique which is robust to various kinds of data manipulation. Intellectual property rights information is encoded using a convolutional code, and block-interleaving technique is applied to prevent successive loss of encoded data. Encoded intelloctual property rithts informationis embedded using spread spectrum technique which is robust to cata manipulation. In order to reconstruct intellectual property rights information, watermark signalis detected by covariance between watermarked image and pseudo rando noise sequence which is used to einbed watermark. Embedded intellectual property rights information is obtaned by de-interleaving and cecoding previously detected wtermark signal. Experimental results show that block interleaving watermarking technique can detect embedded intellectial property right informationmore correctly against to attacks like Gaussian noise additon, filtering, and JPEG compression than general spread spectrum technique in the same PSNR.

• The Journal of the Acoustical Society of Korea
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• v.38 no.2
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• pp.207-213
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• 2019

In this paper, we evaluate the communication performance of convolutional code with block interleaving in a frequency-selective channel. Block interleaving is a technique for spreading and rearranging digital data streams. A block interleaving technique is applied to improve the performance by dispersing the concentration of burst errors in a frequency-selective channel. As a result of evaluating the performance of the convolutional code with block interleaving in the water tank experiment, There was no difference in the performance of convolutional codes using block interleaving in a frequency-selective channel. However, in the frequency-selective channel, the convolutional code with block interleaving has a gain of 2dB, and it is confirmed that the underwater acoustic communication performance is improved.

• Journal of Convergence for Information Technology
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• v.7 no.6
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• pp.167-172
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• 2017

In this paper, we propose a variable RGB interleaving technique for efficient data transmission in LED based visible light communication system. Visible light communication systems that utilize light as a resource for data transmission are affected by the nature of light and the three primary colors of light. However, the nature of light, such as light reflection, diffraction, and superposition, causes interference of the data to be transmitted, causing burst errors in the data. Such a problem causes the BER performance of the visible light communication system to degrade. To solve these problems, this paper attempts to utilize the variable RGB interleaving technique. Through variable RGB interleaving, data burst errors can be reduced and inter channel interference in a visible light communication system can be reduced. In addition, if the proposed system is applied to meet the QoS that depends on the importance of data or the requirements of the user, it can provide QoS requested by the user and enable efficient data transmission.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.36-46
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• 2017

The turbo code, an error correction code, needs a long decoding time since the same decoding process must be repeated several times in order to obtain a good BER performance. Thus, parallel processing may be used to reduce the decoding time, in which case there may be a memory contention that requires additional buffers. The QPP interleaving has been proposed to avoid such case, but there is still a possibility of memory contention when a decoder is constructed using the so-called double flow technique. In this paper, we propose an even-odd cross mapping technique to avoid memory conflicts even in decoding using the double-flow technique. This method uses the address generation characteristic of the QPP interleaving and can be used to implement the interleaving circuit between the decoding blocks and the LLR memory blocks. When the decoder implemented by applying the double flow and the proposed methods is compared with the decoder by the conventional MDF techniques, the decoding time is reduced by up to 32% with the total area increase by 8%.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.2
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• pp.96-105
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• 2021

Large-scale power converters consist of series or parallel module combinations. In these modular converter systems, the interleaving technique can be applied to improve capacitor reliability by reducing the ripple of the I/O current in which each module operates as a phase difference. However, when applying the interleaving technique for conventional three-level boost converters, the short-circuit period of the converter can be an obstacle. Such problem is caused by the absence of a low-level inductor of the conventional three-level boost converter. To solve this problem, a three-level boost converter with a low-level inductor is proposed and analyzed to enable interleaved operation. In the proposed circuit, the current ripple of the output capacitor depends on the neutral point connections between the modules. In this study, the ripple current is analyzed by the neutral point connections of the three-level boost converter that has a low-level inductor, and the effectiveness of the proposed circuit is proven by simulation and experiment.