• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.4
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• pp.294-297
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• 2018

This paper analyzes the losses of the switching device for a full bridge inverter connected to the grid. As the development of power conversion system, losses are dominant factors in judging the efficiency of a system. The losses of a switching device can be divided into switching loss and conduction loss, both of which can be estimated by analyzing periodic switching waveform. The switching loss is generated when the switch is turned on and off, while the conduction loss is generated when the switch is turned on. The estimated losses of the MOSFET switch are compared with the simulation results.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1325-1335
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• 2018

This paper presents a discontinuous pulse width modulation (DPWM) method to reduce switching losses in an indirect matrix converter (IMC) drive. The IMC has a number of power semiconductor switches. In other words, it consists of a rectifier stage and an inverter stage for AC/AC power conversion, which are composed of 12 and 6 switching devices, respectively. Therefore, the switching devices of the IMC suffer from high switching losses in the IMC drives. Various topologies to reduce switching losses have been studied by eliminating a number of switches from the rectifier stage. In this study, in contrast to prior research, a DPWM method is presented to reduce the switching losses of the inverter stage. The effectiveness of the proposed method to reduce switching losses in IMC drives is verified by simulations and experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.2
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• pp.173-183
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• 2014

In this paper, an analysis of power losses for the three-level T-type and neutral-point clamped (NPC) PWM inverters is presented, in which the conduction and switching losses of semiconductor devices of the inverters are taken into account. In the inverter operation, the conduction loss depends on the modulation index (MI) and power factor (PF), whereas the switching loss depends on the switching frequency. Power losses for the T-type and NPC inverters are analyzed and calculated at the different operating points of MI, PF and the switching frequency, in which the four different models of semiconductor devices are adopted. In the case of lower MI, the NPC-type is more efficient than the T-type, and vice versa. The validity of the power loss analysis has been verified by the simulation results.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.3
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• pp.76-81
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• 2002

In high power motor drive system, the hard-switching topology produces severs switching losses and EMI noises. Also the inverter switching frequency is thus limited because of excessive loss and thermal handling problem. The primary purpose of the proposed works on the induction motor drive system is to develop an advanced soft-switching inverter topology that is most suitable for high power induction motor drive applications. To make the optimal selection EMI comparison of the switching losses presented. To verify the proposed design procedure, detailed simulation analysis with theoretical and experimental approaches have been done using laboratory prototype.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.101-102
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• 2017

This paper presents analysis of losses of switching device for full bridge inverter connected to grid. The losses are a dominant factor that judges efficiency of the system. The losses of switching device are divided to switching loss and conduction loss. They are can be estimated by analyzing periodic switching waveforms. The switching loss is generated at the point that turn-on and off. And the conduction loss is generated while the switch is on condition. The estimated losses of switch are compared to simulation result in this paper.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.738-750
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• 2017

In this paper, carrier-based pulse width modulation (CBPWM), space vector PWM (SVPWM) and reduced switching losses PWM (RSLPWM) for the three-level neutral point clamped (NPC) inverter are introduced. In the case of the neutral point (NP) potential (NPP) offset, an asymmetric disposition PWM (ASPDPWM) strategy is proposed, which can output PWM sequences correctly and suppress the lower order harmonics of the inverter effectively. An NPP balance strategy based on carrier based PWM (CBPWM) is analyzed. A hybrid modulation strategy combining RSLPWM and the NPP balance based on CBPWM is proposed, and hysteresis control is adopted to switch between the two modulation strategies. An experimental prototype of the three-level NPC inverter is built. The effectiveness of the hybrid modulation is verified with a resistance-inductance load and a permanent magnetic synchronous motor (PMSM) load, respectively. The experimental results show that reduced switching losses and an acceptable NPP can be effectively achieved in the hybrid modulation strategy.

• Journal of Power Electronics
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• v.4 no.2
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• pp.77-86
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• 2004

This paper presents a novel three-phase power module bridge type auxiliary resonant AC link snubber for the three-phase voltage-fed sinwave soft switching PWM inverter operating under specific instantaneous space voltage vector modulation. The operating principle of this resonant snubber is described for current source load model during one switching period, along with its design approach based on the simulation data. The performance evaluations of space vector modulation three-phase sinewave soft switching inverter with a new three-phase active auxiliary resonant AC link snubber are discussed as compared with those of three-phase voltage source-fed sinewave hard switching PWM inverter with a standard space voltage vector modulation strategy. The power loss analysis and conventional efficiency estimation of three-phase soft switching PWM inverter using ICBT modules are carried out including all the conduction power losses based upon the measured v-i characteristics of IGBT and its antiparallel diode as well as their switching losses.

• Proceedings of the KIEE Conference
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• 2004.10a
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• pp.207-209
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• 2004

The conventional pulse width modulation dc to at inverters have a defect that all power devices are switched at high switching frequency. Therefore switching losses are significant. This paper proposed a dual-stage inverter that full bridge switches are operating at low output frequency while a high switching frequency are performed by a pre-inverter switch. The proposed inverter is shown to have small switching losses. Simulation and experiments are performed for verification.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.3
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• pp.273-279
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• 2015

A zero vector selection method to reduce switching losses for model predictive control (MPC) of voltage source inverter is proposed. A conventional MPC of voltage source inverter has not been proposed, and a method to select the redundancy of the zero vector is required for this study. In this paper, the redundancy of the zero vectors is selected with generating a zero sequence voltage to reduce switching losses. The zero vector of 2-level inverter is determined by determining sign of the zero sequence voltage. In the proposed method, the quality of the current is retained and switching loss can be reduced compared with the conventional method. This result was verified by P-sim simulation and experiments.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1610-1620
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• 2015

A major problem in conventional multilevel inverter is that an increase in power semiconductor switches causes an increase in cost and switching losses of the inverter. The multicarrier strategy adopted for the multilevel inverters has become more popular due to reduced cost, lower harmonic distortion, and higher voltage capability than the conventional switching strategy applied to inverters. Various topologies and modulation strategies have been reported for utility and drive applications. Level shifted based pulse width modulation techniques are proposed to investigate the performance of the multilevel inverter. The proposed work focuses on reducing the utilized switches so that the cost and the switching losses of the inverter do not go up and the consistent efficiency could be achieved. This paper presents the detailed analysis of these topologies. The analysis is based on the number of switches, DC sources, output level, maximum voltage, and the efficiency. As an illustration, single phase cascaded multilevel inverter topologies are simulated using MATLAB/SIMULINK and the experimental results demonstrate the viability of these inverters.