• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.8
• /
• pp.1719-1724
• /
• 2004

In this paper, we have proposed a new structure of LDMOST, which has been expected as a next generation RF power device, to improve the BV(Breakdown Voltage) characteristics. The proposed structure, named external field ring, is formed around a drift region by the three dimensional structure. The external field ring relieves the electric field in the drift region and improves the BV characteristics. By the three dimensional TCAD simulations, it was found that the BV of LDMOST was increased by the increase of the junction depth and doping concentration of the external field ring. Therefore, the BV characteristics of the LDMOST can be remarkably improved by addition of external field ring using an existing p+ sinker process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.7
• /
• pp.667-674
• /
• 2005

In this paper the gate overlap length of the LDMOST is optimized for obtaining longer device lifetime. The LDMOSI device with drift region is fabricated using the $0.25\;{\mu}m$ CMOS Process. The gate overlap lengths on drift region are $0.1\;{\mu}m,\;0.4\;{\mu}m\;0.8\;{\mu}m\;and\;1.1\;{\mu}m$, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with gate overlap length of $0.4\;{\mu}m$ showed the longest on-resistance lifetime, 0.02 years and breakdown voltage of 22 V and on-resistance of $23\;m\Omega{\cdot}mm^2$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.19 no.11
• /
• pp.994-999
• /
• 2006

For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a $0.25{\mu}m$ standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.

• Proceedings of the KIEE Conference
• /
• 2005.11a
• /
• pp.57-59
• /
• 2005

전력용 IC에서 높은 항복전압의 구현을 위해서 RESURF구조가 많이 사용되고 있다. 하지만 하나의 칩 위에서 다양한 항복전압을 가지는 소자를 구현하기 위해서는 에피층의 농도가 각각 달라져야하는데 이는 공정상의 복잡함과 비용의 문제를 수반하게 된다. 이런 문제점에 따라 본 연구에서는 전력용 IC에서 항복전압이 다른 다수의 LDMOST를 추가 공정없이 에피 영역의 길이를 조절하여 구현할 수 있음을 해석적인 방볍과 2차원 소자 시뮬레이터를 이용하여 확인하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.23 no.9
• /
• pp.667-670
• /
• 2010

In this paper, a high voltage current sensing circuit for boost converter is designed and verified by Cadence SPECTRE simulations. The current mirror pair, power and sensing metal-oxide semiconductor field effect transistors (MOSFETs) with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side lateral-diffused MOS transistor (LDMOST) switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35 ${\mu}m$ BCD process show that current sensing is accurate and the pulse frequency modulation (PFM) boost converter using the proposed current sensing circuit satisfies with the specifications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.14-14
• /
• 2010

A high voltage current sensing circuit for LED driver IC is designed and verfied by Cadence SPECTRE simulations. The current mirror pair, power and sensing MOSFETs with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side LDMOST switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35um BCD process show that current sensing is accurate with properly frequency compensated opamp.