• Journal of IKEEE
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• v.20 no.1
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• pp.119-122
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• 2016

In this paper, we propose LDO regulator to operate using Pseude resistor instead of widely used Feedback resistor in conventional LDO regulator. Proposed Feedback network using Pseudo resistor has smaller area than the conventional feedback resistor and plays the role of an conventional LDO regulator. Thus, it has been proposed to compensate for the disadvantages of LDO regulator with noise. Although proposed LDO regulator compared with conventional LDO regulator has similar performance, this LDO regulator provide higher efficiency by reducing the overshoot and decreasing the area. This circuit was designed to using a Dongbu Hitek 0.18um CMOS process.

• Journal of IKEEE
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• v.20 no.3
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• pp.265-272
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• 2016

A SCALDO(Supercapacitor Assisted LDO) regulator is a newly studied regulator to improve the efficiency of a LDO regulator. Commonly a LDO regulator has very low efficiency and a SCALDO regulator can improve it considerably because this regulator can reuse meaninglessly wasted energy at the LDO regulator by a supercapacitor witch is attached between input and a LDO regulator. However this regulator has several challenges because it is a being studied regulator. One of them is an overvoltage issue. At initial operating of this regulator, a supercapacior is totally discharged and input is connected with a supercapacitor and a LDO regulator in series. Thus, input voltage is enabled to a LDO regulator and this input voltage is a significant value to a LDO regulator because commonly input voltage is bigger than twice output voltage. In this paper, to solve this overvoltage issue, we proposed a new SCALDO regulator that has a pre-charger for charging a supercapacitor before starting operation. And we found that a proposed SCALDO regulator can properly reduce overvoltage of a LDO regulator through experiments.

• Journal of IKEEE
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• v.20 no.3
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• pp.307-309
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• 2016

In this paper, we propose LDO regulator with improved transient using a simple feedback structure in conventional LDO regulator. This proposed circuit has the feedback structure which reduces the response time of overshoot appeared in the output of conventional LDO regulator. Therefore, this LDO regulator can be a more stable operation. Thus, the proposed feedback structure is to operate such as conventional LDO regulator without changing the area, it complements the disadvantage of LDO regulator with noise in the output. This circuit was designed to using a Dongbu Hitek 0.18um CMOS process.

• Journal of IKEEE
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• v.23 no.2
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• pp.552-556
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• 2019

This paper present a capless low drop out regulator (LDO) that improves the load transient response characteristics by using a current regulator. A voltage regulator circuit is placed between the error amplifier and the pass transistor inside the LDO regulator to improve the current characteristics of the voltage line, The proposed fast transient LDO structure was designed by a 0.18 um process with cadence's virtuoso simulation. according to test results, the proposed circuit has a improved transient characteristics compare with conventional LDO. the simulation results show that the transient of rising increases from 1.954 us to 1.378 us and the transient of falling decreases from 19.48 us to 13.33 us compared with conventional capless LDO. this Result has improved response rate of about 29%, 28%.

• Journal of IKEEE
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• v.27 no.3
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• pp.258-264
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• 2023

This paper proposes an LDO regulator with a built-in ESD (Electro Static Discharge) protection circuit to effectively operate and prevent destruction of the LDO (Low Drop Out) regulator according to the load current. The proposed LDO regulator can more effectively adjust the gate node voltage of the pass transistor according to the output voltage of the LDO regulator by using an additional feedback current circuit structure. In addition, it is expected to have high reliability for the ESD situation by embedding a new structure that increases the holding voltage by about 2V by reducing the current gain on the SCR loop by adding a P+ bridge to the existing ESD protection device.

• Journal of IKEEE
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• v.25 no.1
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• pp.201-205
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• 2021

In this paper present Low Drop-Out (LDO) regulator that improved load transient characteristics due to the push-pull detection structure. The response characteristic of the voltage delta value is improved due to the proposed push-pull sensing circuit structure between the input terminal of the LDO regulator pass transistor and the output terminal of the internal error amplifier. Voltage value has improved load transient characteristics than conventional LDO regulator. Compared to the conventional LDO regulator, it has an improved response speed of approximately 244 ns at rising time and approximately 90 ns at falling time. The proposed circuit was simulated by the samsung 0.13um process using Cadence's Specter and Virtuoso simulator.

• Journal of IKEEE
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• v.24 no.4
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• pp.1162-1166
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• 2020

In this paper Low Drop-Out (LDO) regulator that improved load regulation characteristics due to the feedback detection structure. The proposed feedback sensing circuit is added between the output of the LDO's internal error amplifier and the input of the pass transistor to improve the regulation of the delta value coming into the output. It has a voltage value with improved load regulation characteristics than existing LDO regulator. The proposed LDO structure was analyzed in Samsung 0.13um process using Cadence's Virtuoso, Spectre simulator.

• Journal of IKEEE
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• v.26 no.1
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• pp.124-128
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• 2022

Conventional LDO regulator external capacitors can reduce transient response characteristics such as overshoot and undershoot. However, the capacitorless LDO regulator proposed in this study applied body technology to the pass transistor to improve the transient response and provide excellent current drive capability. The operating conditions of the proposed LDO regulator are set to an input voltage that varies from 3.3V to 4.5V, a maximum load current of 200mA, and an output voltage of 3V. As a result of the measurement, it was found that when the load current was 100 mA, the voltage was 95 mV in the undershoot state and 105 mV in the overshoot state.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.34-40
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• 2011

This paper presents a low-dropout (LDO) linear regulator using ultra-low output impedance buffer for frequency compensation. The proposed buffer achieves ultra low output impedance with dual shunt feedback loops, which makes it possible to improve load and line regulations as well as frequency compensation for low voltage applications. A reference control scheme for programmable output voltage of the LDO linear regulator is presented. The designed LDO linear regulator works under the input voltage of 2.5~4.5V and provides up to 300mA load current for an output voltage range of 0.6~3.3V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.7
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• pp.993-1000
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• 2018

This paper proposes a low-dropout voltage regulator(LDO) using self-cascode structure. The self-cascode structure was optimized by adjusting the channel length of the source-side MOSFET and applying a forward voltage to the body of the drain-side MOSFET. The self-cascode of the input differential stage of the error amplifier is optimized to give higher transconductance, but the self-cascode of the output stage is optimized to give higher output resistance, The proposed LDO using self-cascode structure was designed by a $0.18{\mu}m$ CMOS technology and simulated using SPECTRE. The load regulation of the proposed LDO regulator was 0.03V/A, whereas that of the conventional LDO was 0.29V/A. The line regulation of the proposed LDO regulator was 2.23mV/V, which is approximately three times improvement compared to that of the conventional LDO. The transient response of the proposed LDO regulator was 625ns, which is 346ns faster than that of the conventional LDO.