• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.1
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• pp.51-58
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• 2014

A LFSR is commonly used for various stream cryptography applications to generate random numbers. A Leap-ahead LFSR was presented to generate a multi-bits random number per cycle. It only requires a single LFSR and it has an advantages in hardware complexity. However, it suffers from the significant reduction of maximum period of the generated random numbers. This paper presents the new segmented Leap-ahead LFSR to solve this problem. It consists of two segmented LFSRs. We prove the efficiency of the proposed segmented architecture using the precise mathematical analysis. We also demonstrate the proposed comparison results with other counterparts using Xinilx Vertex5 FPGA. The proposed architecture can increase 2.5 times of the maximum period of generated random numbers compared to the typical Leap-ahead architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.7
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• pp.1577-1584
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• 2015

In this paper, we propose a method for generating pattern classifier based on LFSR. The proposed pattern classifier bosed on LFSR is easy to see non-reachable state, and we can obtain dependency vector by using the 0-basic path. Also, we propose a method for generating pattern classifiers based on LFSR which correspond to given dependency vector.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.326-329
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• 2017

Most modern computer communications and storage media support encryption technology. Many of the Ping Pong algorithms are stream ciphers that generate random numbers in the LFSR core structure. The LFSR has a structure that guarantees the maximum period of a given size, but it has a linear structure and can be predicted. Therefore, the Ping Pong algorithm has a feature of making the linearity of the LFSR into a nonlinear structure through variable clocks and functions. In this paper, we try to improve the existing linearity by replacing the linear disadvantages of LFSR with logistic maps.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.343-346
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• 2009

Since an LFSR as a pattern generator has solely linear dependency in itself, it generates sequences by moving the bit positions for a pattern generation. So the correlation between the generated patterns is high and thus reduces the possibility of fault detection. To overcome these problems many researchers have studied to have goodness of randomness between the output test patterns. In this paper, we propose the new and effective method to construct phase shifter as PRPG.

• Convergence Security Journal
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• v.12 no.4
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• pp.17-23
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• 2012

Recently, the research for cryptographic algorithm, in particular, a stream cipher has been actively conducted for wireless devices as growing use of wireless devices such as smartphone and tablet. LFSR based random number generator is widely used in stream cipher since it has simple architecture and it operates very fast. However, the conventional multi-LFSR RNG (random number generator) suffers from its hardware complexity as well as very closed correlation between the numbers generated. A leap-ahead LFSR was presented to solve these problems. However, it has another disadvantage that the maximum period of the generated random numbers are significantly decreased according to the relationship between the number of the stages of the LFSR and the number of the output bits of the RNG. This paper presents new leap-ahead LFSR architecture to prevent this decrease in the maximum period by applying segmentation technique to the conventional leap-ahead LFSR. The proposed architecture is implemented using VHDL and it is simulated in FPGA using Xilinx ISE 10.1, with a device Virtex 4, XC4VLX15. From the simulation results, the proposed architecture has only 20% hardware complexity but it can increases the maximum period of the generated random numbers by 40% compared to the conventional Leap-ahead archtecture.

• Journal of Korea Society of Industrial Information Systems
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• v.10 no.3
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• pp.57-63
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• 2005

Kim and Fenn et al. proposed two modular AB multipliers based on LFSR(Linear Feedback Shift Register) architecture. These multipliers use AOP, which has all coefficients with '1', as an irreducible polynomial. Thereby, they have good hardware complexity compared to the previous architectures. This paper proposes a modular $AB^2$ multiplier based on LFSR architecture and a modular exponentiation architecture to improve the hardware complexity of the Kim's. Our multiplier also use the AOP as an irreducible polynomial as the Kim architecture. Simulation result shows that our multiplier reduces the hardware complexity about $50\%$ in the perspective of XOR and AND gates compared to the Kim's. The architecture could be used as a basic block to implement public-key cryptosystems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.35-42
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• 2005

This paper proposes a new reseeding methodology using a variable-rank multiple-polynomial linear feedback shift register (MP-LFSR). In the proposed reseeding scheme, a test cube with large number of specified bits is encoded with a high-rank polynomial, while a test cube with a small number of specified bits is encoded with a low-rank polynomial. Therefore, according to the number of specified bits in each test cube, the size of the encoded data can be optimally reduced. A variable-rank MP-LFSR can be implemented with a slight modification of a conventional MP-LFSR and Multiple Polynomial can be represented by adding just 1 bit to encoding data. The experimental results on the largest ISCAS'89 benchmark circuits show that the proposed methodology can provide much better encoding efficiency than the previous methods with adequate hardware overhead.

• Convergence Security Journal
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• v.15 no.2
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• pp.81-89
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a key scheduler that employs the presented LFSR and reverse LFSR that can generate four outputs simultaneously. In addition, we construct new key scheduler that generates 4 subkey bytes at a clock since each round block requires 4 subkey bytes at a time. Thus, the entire HIGHT processor can be controlled by single system clock with regular control mechanism. We synthesize the HIGHT processor using the VHDL. From the synthesis results, the logic size of the presented key scheduler can be reduced as 9% compared to the counterpart that is employed in the conventional HIGHT processor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.6
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• pp.1150-1156
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• 2009

In this paper, we propose the gradual encryption method of image using LFSR(Linear Feedback Shift Register) and 2D CAT(Two-Dimensional Cellular Automata Transform). First, an LFSR is used to create a PN(pseudo noise) sequence, which is identical to the size of the original image. Then the created sequence goes through an XOR operation with the original image resulting to the first encrypted image. Next, the gateway value is set to produce a 2D CAT basis function.The created basis function multiplied with the first encrypted image produces the 2D CAT encrypted image which is the final output. Lastly, the stability analysis verifies that the proposed method holds a high encryption quality status.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.973-979
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• 2002

In this paper, an efficient architecture for the finite field multiplier is proposed. This architecture is faster and smaller than any other LFSR architectures. The traditional LFSR architecture needs t x m registers for achieving the t times speed. But, we designed the multiplier using a novel fast architecture without increasing the number of registers. The proposed multiplier is verified with a VHDL description using SYNOPSYS simulator. The measured results show that the proposed multiplier is 2 times faster than the serial LFSR multiplier. The proposed multiplier is expected to become even more advantageous in the smart card cryptography processors.