• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.22-25
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• 2001

A new mesh-topology model of IGBT is presented. It can be applied to the research of IGBT's static and dynamic latch-up (du/dt latch-up, overheat latch-up, overload latch-up, overvoltage latch-up) as well as the switching on-off behavior of the device. The overcurrent latch-up is analyzed.

• 한국전기전자재료학회논문지
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• 제17권8호
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• pp.799-805
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• 2004

Two dimensional MEDICI simulator is used to study the characteristics of latch-up current of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics, latch-up current density, ON-voltage drop and electrical property with the variations of p-base impurity concentrations. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have the better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer p-base structure under the floating $N^+$ emitter indicates to have the better characteristics of latch-up current and breakover voltage.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.339-341
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• 1997

From this first studies, We have investigated the latch-up characteristics of various CMOS well structures possible with high energy ion implantation processes. In this study, we also investigated those of STI(Shallow Trench Isolation} structures with varing n+/p+ spacing and the depth of trench. STI structure is formed by T-SUPREM4 process simulator, and then latch-up simulations for each case were performed by MEDICI device simulator for latch-up immunity improvement. STI is very effective to preventing the degradation of latch-up characteristics as the n+/p+ spacing is reduced. These studies will allow us to evaluate each technology and suggest guidelines for the optimization of latch-up susceptibility.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.441-444
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• 1998

This paper is concerned with researching latch-up immune CMOS structure was performed. By the simulation results, the connecting layer had more effect than the buried layer to latch-up immune. When the connecting layer was the dose 1*10$^{14}$ /cm$^{2}$ and the energy 500KeV, the trigger current was more 0.6mA/.mu.m and the trigger voltage was 6V. The more the connecting layer dose was lower, the more the latch-up immune characteristics was butter.

• 한국통신학회논문지
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• 제17권8호
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• pp.898-907
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• 1992

본 논문은 latch-up의 가능성을 최소화하는 여러가지 방법 중 공정이나 재질 변겨에 의한 방법이 아닌, mask의 layout 변경에 의한 latch-up 최소화 방법에 대하여 기술하였다. 기존의 공정이나 재질 변경에 의한 방법이 어려운 공정이나 특수 시설 사용을 전제로 하고 있는 반면, mask의 layout 변경에 의한 방법은 기존의 공정을 그대로 사용할 수 있는 장점을 갖고 있다. Layout 변경에 의한 latch-up 최소화 방법 수행을 위하여 substrate의 N+와 S-W접합(substrate-well 접합 )사이의 거리를 a, S-W 접합에서 well의 P+까지의 거리를 b로 하여 a와 b가 다른 6개의 latch-up model과 guard ring 구조를 갖는 3개의 latch-up 모델을 만들어 latch-up관련 변수에 대하여 비교 검토 하였다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 춘계학술대회
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• pp.719-721
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• 2012

본 시험은 군전자장비의 전원제어부품으로 사용되는 TPS54315소자에 대하여 과도방사선에 따른 과도응답특성인 Upset/Latch-up특성을 평가하기 시험으로 포항가속기 연구소내의 Test LINAC 조사시설을 이용하여 $1.43{\times}10^7$rad(si)/sec~$1.25{\times}10^8$rad(si)/sec 선량률 조건에서의 실측시험을 수행하였다. 시험결과 $1.0{\times}10^8$rad(si)/sec 이후 Latch-up 현상이 확인되었으며 연속펄스 인가 시 Latch-up상태에서 정상상태로 복귀하는 결과를 확인하였다. 또한 이러한 현상은 과도방사선에 의한 광전류가 내부전원 Reset로직을 트리거 시킴으로써 Latch-up상태에서의 전원바이어스를 일시적으로 차단함에 따라 발생된 것으로 본 실험을 통하여 Reset회로가 내장된 소자의 경우 일부 Latch-up현상과 동시에 Reset회로가 트리거 되는 경우 Latch-up상태에서 정상상태로 복귀되는 결과를 확인하였다.

• 한국전기전자재료학회논문지
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• 제27권9호
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• pp.551-554
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• 2014

This paper was showed latch up characteristics of super junction power MOSFET by parasitic thyristor according to trench etch angle. As a result of research, if trench etch angle of super junction MOSFET is larger, we obtained large latch up voltage. When trench etch angle was $90^{\circ}$, latch up voltage was more 50 V. and we got 700 V breakdown voltage. But we analyzed on resistance. if trench etch angle of super junction MOSFET is larger, we obtained high on resistance. Therefore, we need optimal point by simulation and experiment for solution of trade off.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.283-285
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• 2001

In this paper, a new lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n+ cathode region. The improvement of latch-up performance is verified using the two-dimensional simulator MEDICI and the simulation results on the latch-up current density are 3.12${\times}$10$\^$-4/ A/$\mu\textrm{m}$ for the proposed LIGBT and 0.94${\times}$10$\^$-4/ A/$\mu\textrm{m}$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.164-167
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• 1994

In this Study, we design the process of 0.1$\mu\textrm{m}$ gate length CMOS that is immunized against Latch-up, and investigate the characteristic of Latch-up of this device by the design rule of layout. Using TSUPREM4 and MEDICI, we design the device and simulate the variable characteristics of it we could understand that the characteristic of Latch-up is changed for the better by varying the critical factor of it. We also investigate the structure of CMOS that can be immunized against Latch-up.

• 대한전자공학회논문지
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• 제22권5호
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• pp.50-56
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• 1985

A common failure mechanism in bulk CMOS integrated circuits is the latch-up of parasitic SCR structure inherent in the bulk CMOS structure. Latch-up triggering and holding charac-teristics have been measured in the test devicrs which include conventional and Schottky-damped CMOS structures with various well depths and n+/p+ spacings. It is demonstrated that Schottky-clamped CMOS is more latch-up immune than conventional bulk CMOS. Finally, the simulation results by circuit simulation program (SPICE) are compared with measured results in order to verify the validity of the latch-up modal composed of nan, pnp transistors and two external resistors.