• Journal of the Chungcheong Mathematical Society
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• v.34 no.3
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• pp.221-234
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• 2021

We introduce high-order Hopfield neural networks with Leakage delays. Furthermore, we study the uniqueness and existence of Hopfield artificial neural networks having the weighted pseudo almost periodic forcing terms on finite delay. Our analysis is based on the differential inequality techniques and the Banach contraction mapping principle.

• Journal of the Chungcheong Mathematical Society
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• v.35 no.1
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• pp.39-52
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• 2022

We introduce Clifford-valued neural networks with leakage delays. Furthermore, we study the uniqueness and existence of Clifford-valued Hopfield artificial neural networks having the Stepanov weighted pseudo almost periodic forcing terms on leakage delay terms. However the noncommutativity of the Clifford numbers' multiplication made our investigation diffcult, so our results are obtained by decomposing Clifford-valued neural networks into real-valued neural networks. Our analysis is based on the differential inequality techniques and the Banach contraction mapping principle.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.17-25
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• 2016

This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $4{\times}4$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.131-144
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• 2015

An extensive investigation of the influence of gate engineering on the CNTFET switching, high frequency and circuit level performance has been carried out. At device level, the effects of gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. It is revealed that hetero - material - gate CNTFET(HMG - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, and is more suitable for use in low power and high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the performance parameters of circuits have been calculated and the optimum combinations of ${\Phi}_{M1}/{\Phi}_{M2}/{\Phi}_{M3}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product(PDP). We show that, compared to a traditional CNTFET - based circuit, the one based on HMG - CNTFET has a significantly better performance (SNM, energy, PDP). In addition, results also illustrate that HMG - CNTFET circuits have a consistent trend in delay, power, and PDP with respect to the transistor size, indicating that gate engineering of CNTFETs is a promising technology. Our results may be useful for designing and optimizing CNTFET devices and circuits.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.59-65
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• 2013

Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn't require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.

• Restorative Dentistry and Endodontics
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• v.46 no.1
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• pp.3.1-3.14
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• 2021

Objectives: This study aimed to evaluate the interface between a calcium silicate cement (CSC), Biodentine and dental adhesives in terms of sealing ability. Materials and Methods: Microleakage test: 160 standardized class II cavities were prepared on 80 extracted human molars. The cavities were filled with Biodentine and then divided into 2 experimental groups according to the time of restoration: composite resin obturation 15 minutes after Biodentine handling (D0); restoration after 7 days (D7). Each group was then divided into 8 subgroups (n = 5) according to the adhesive system used: etch-and-rinse adhesive (Prime & Bond); self-etch adhesive 2 steps (Optibond XTR and Clearfil SE Bond); self-etch adhesive 1 step (Xeno III, G-aenial Bond, and Clearfil Tri-S Bond); and universal used as etch-and-rinse or self-etch (ScotchBond Universal ER or SE). After thermocycling, the teeth were immersed in a silver nitrate solution, stained, longitudinally sectioned, and the Biodentine/adhesive percolation was quantified. Scanning electron microscopic observations: Biodentine/adhesive interfaces were observed. Results: A tendency towards less microleakage was observed when Biodentine was etched (2.47%) and when restorations were done without delay (D0: 4.31%, D7: 6.78%), but this was not significant. The adhesives containing 10-methacryloyloxydecyl dihydrogen phosphate monomer showed the most stable results at both times studied. All Biodentine/adhesive interfaces were homogeneous and regular. Conclusions: The good sealing of the CSC/adhesive interface is not a function of the system adhesive family used or the cement maturation before restoration. Biodentine can be used as a dentine substitute.

• Advances in nano research
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• v.15 no.6
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• pp.521-531
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• 2023

Quantum-dot cellular automata (QCA) has shown great potential in the nanoscale regime as a replacement for CMOS technology. This work presents a specific approach to static random-access memory (SRAM) cell based on 2:1 multiplexer, 4-bit SRAM array, and 32-bit SRAM array in QCA. By utilizing the proposed SRAM array, a single-layer 16×32-bit SRAM with the read/write capability is presented using an optimized signal distribution network (SDN) crossover technique. In the present study, an extremely-optimized 2:1 multiplexer is proposed, which is used to implement an extremely-optimized SRAM cell. The results of simulation show the superiority of the proposed 2:1 multiplexer and SRAM cell. This study also provides a more efficient and accurate method for calculating QCA costs. The proposed extremely-optimized SRAM cell and SRAM arrays are advantageous in terms of complexity, delay, area, and QCA cost parameters in comparison with previous designs in QCA, CMOS, and FinFET technologies. Moreover, compared to previous designs in QCA and FinFET technologies, the proposed structure saves total energy consisting of overall energy consumption, switching energy dissipation, and leakage energy dissipation. The energy and structural analyses of the proposed scheme are performed in QCAPro and QCADesigner 2.0.3 tools. According to the simulation results and comparison with previous high-quality studies based on QCA and FinFET design approaches, the proposed SRAM reduces the overall energy consumption by 25%, occupies 33% smaller area, and requires 15% fewer cells. Moreover, the QCA cost is reduced by 35% compared to outstanding designs in the literature.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.