• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.11
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• pp.635-639
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• 2016

In the devices used in the microwave frequency band, the gain decreases as the frequency increases due to the parasitic component. To compensate for these characteristics, a linear gain equalizer with an opposite slope is needed in wideband systems, such as those used for electronic warfare. In this study, a linear gain equalizer that can be used in the 18 ~ 40GHz band is designed and fabricated. Circuit design and momentum design (optimizations) were carried out to reduce the errors between design and manufacturing. A thin film process is used to minimize the parasitic components within the implementation frequency band. A sheet resistance of 100 ohm/square was employed to minimize the wavelength variation due to the length of the thin film resistor. This linear gain equalizer is a structure that combines a quarter wavelength-resonator on a series microstrip line with a resistor. All three 1/4 wavelength short resonators were used. The fabricated linear gain equalizer has a loss of more than -5dB at 40GHz and a 6dB slope in the 18 ~ 40GHz band. By using the manufactured gain equalizer in a multi-stage connected device such as an electronic warfare receiver, the gain flatness degradation with increasing frequency can be reduced.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.10
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• pp.59-64
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• 2008

In this paper an adjustable linear gain equalizer which is operated from 6GHz to 18GHz in order to apply wideband RF circuit System is proposed and fabricated on $Al_2O_3$ substrate using thin film process. An adjustable linear gain equalizer is proposed to T type circuit and designed to aim on variable slope $-7dB{\sim}-13dB$ using the PIN Diode

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.11
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• pp.1053-1060
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• 2016

This paper proposes an adaptive equalizer with the digitally controlled active variable capacitor. An equalizing amplifier consists of a main amplifier and a source degeneration RC filter which is implemented using the digitally controlled active variable capacitor for area efficiency and linear loss compensation. The active capacitor changes its capacitance by the amplifier gain control, which is based on miller effect. In the simulated results, the proposed equalizer compensates the high frequency loss and extends the data eye width from 0.31 UI to 0.64 UI.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.71-79
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• 2013

This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver adapts to channel and chip process variation by adaptation circuit using sampler and serializer. The adaptation principle is explained. It describes technique receiving ground referenced differential signal of voltage-mode transmitter for low-power. The CTLE(Continuous Time Linear Equalizer) having 17.6 dB peaking gain to remove long tail ISI caused channel with -21 dB attenuation. The voltage margin is 210 mV and the timing margin is 0.75 UI in eye diagram. The receiver consumes 0.87 mW/Gb/s low power in 45 nm CMOS technology.

• Journal of Communications and Networks
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• v.12 no.5
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• pp.442-448
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• 2010

Cooperative relaying methods have attracted a lot of interest in the past few years. A conventional cooperative relaying scheme has a source, a destination, and a single relay. This cooperative scheme can support one symbol transmission per time slot, and is caned full rate transmission. However, existing fun rate cooperative relay approaches provide asymmetrical gain for different transmitted symbols. In this paper, we propose a cooperative relaying scheme that is assisted with dual relays and provides full transmission rate with the same macro-diversity to each symbol. We also address equalization for the dual relay transmission system in addition to addressing the issues concerning the improvement of system performance in terms of optimal power allocations.

• Journal of Communications and Networks
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• v.14 no.3
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• pp.273-279
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• 2012

In this paper, we propose an iterative interstream interference cancellation technique for system with frequency selective multiple-input multiple-output (MIMO) channel. Our method is inspired by the fact that the cancellation of the interstream interference can be regarded as a reduction in the magnitude of the interfering channel. We show that, as iteration goes on, the channel experienced by the equalizer gets close to the single input multiple output (SIMO) channel and, therefore, the proposed SIMO-like equalizer achieves improved equalization performance in terms of normalized mean square error. From simulations on downlink communications of $2{\times}2$ MIMO systems in high speed packet access universal mobile telecommunications system standard, we show that the proposed method provides substantial performance gain over the conventional receiver algorithms.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.1
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• pp.123-132
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• 1999

In this paper, a quadratic sigmoid neural equalizer(QSNE) is proposed to improve the performance of conventional neural equalizer in terms of bit error probability by using a quadratic sigmoid function as the activation function of neural networks. Conventional neural equalizers which have been used to compensate for nonlinear distortions adopt the sigmoid function. In the case of sigmoid neural equalizer, each neuron has one linear decision boundary. So many neurons are required when the neural equalizer has to separate complicated structure. But in case of the proposed QSNF and quadratic sigmoid neural decision feedback equalizer(QSNDFE), each neuron separates decision region with two parallel lines. Therefore, QSNE and QSNDFE have better performance and simpler structure than the conventional neural equalizers in terms of bit error probability. When the proposed QSNDFE is applied to communication systems and digital magnetic recording systems, it is an improvement of approximately 1.5dB~8.3dB in signal to moise ratio(SNR) over the conventional decision feedback equalizer(DEF) and neural decision feedback equalizer(NDFE). As intersymbol interference(ISI) and nonlinear distortions become severer, QSNDFE shows astounding SNR shows astounding SNR performance gain over the conventional equalizers in the same bit error probability.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2589-2592
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• 2003

In this paper, a robust mixed H$_2$/H$\_$$\infty$/ output feedback control method is applied to the design of loop filter for PLL carrier phase tracking. The proposed method successfully copes with large S-curve slope uncertainty and a significant decision delay in the closed-loop that may exist In modern receivers due to a convolutional decoder or an equalizer. The objective is to design an output feedback controller which minimizes the H$_2$performance while satisfying the H$\_$$\infty$/ performance to guarantee the gain margin and phase margin for linear time invariant(LTI) polytopic uncertain systems. LMIs based approach is given to solve this problem. We can verify the H$\_$$\infty$/ performance satisfaction and minimize the phase detector error through the simulation result.