• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.6
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• pp.9-15
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• 2005

In this research the discharge characteristics of logic gate of the discharge logic gate plasma display panel with the NOT-AND logic function newly designed was analyzed. As for this discharge logic gate a logical output is induced by controlling the voltage between the electrodes using the discharge path. From the experimental result the discharge characteristics of logic gate is influenced by the interrelation of the voltages appling two vertical electrodes. To in the application possibility to large screen PDP, the discharge characteristics by the line resistance of the electrode was evaluated In result it has been inferred that the influence which the drop of voltage by the line resistance of two vertical electrodes exerts on the discharge of the logic gate is minute. Through the experiment, the optimized values of the pulse voltages and the current limitation resistances of each electrode which composed the discharge logic gate were obtained and maximum operation margin of 49[V] was obtained.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.10
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• pp.510-514
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• 2004

In this paper, we analytically examine the voltage transfer function dependent on input conditions for an N-Input NAND Gate. The logic threshold voltage, defined as a voltage at which the input and the output voltage become equal, changes as the input condition changes for a static NAND Gate. The logic threshold voltage has the highest value when all the N-inputs undergo transitions and it has the lowest value when only the last input connected to the last NMOS to ground, makes a transition. This logic threshold voltage difference increases as the number of inputs increases. Therefore, in order to provide a near symmetric voltage transfer function, a multistage N-Input Gate consisting of 2-Input Logic Gates is desirable over a conventional N-Input Gate.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.29-34
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• 2010

This paper proposes a new parity-preserving reversible logic gate. It is a parity-preserving reversible logic gate, that is, the party of the outputs matches that of the inputs. In recent year, reversible logic gate has emerged as one of the important approaches for power optimization with its application in low CMOS design, quantum computing and nono-technology. We show that our proposed parity-preserving reversible logic gate is much better in terms of number of reversible logic gates, number of garbage-outputs and hardware complexity with compared ti the exiting counterpart.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.71-79
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• 1993

This paper proposes a new test pattern generation methodology for combinational logic circuits using neural networks based on a modular structure. The CUT (Circuit Under Test) is described in our gate level hardware description language. By conferring neural database, the CUT is compiled to an ATPG (Automatic Test Pattern Generation) neural network. Each logic gate in CUT is represented as a discrete Hopfield network. Such a neual network is called a gate module in this paper. All the gate modules for a CUT form an ATPG neural network by connecting each module through message passing paths by which the states of modules are transferred to their adjacent modules. A fault is injected by setting the activation values of some neurons at given values and by invalidating connections between some gate modules. A test pattern for an injected fault is obtained when all gate modules in the ATPG neural network are stabilized through evolution and mutual interactions. The proposed methodology is efficient for test generation, known to be NP-complete, through its massive paralelism. Some results on combinational logic circuits confirm the feasibility of the proposed methodology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.04b
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• pp.112-113
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• 2002

Optical bistability can be applied to the optical logic. optical signal processing and optical memory. We have measured the optical bistability of DFB-SOA and demonstrated all-optical OR logic gate using switching characteristics of DFB-SOA.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.42-45
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• 1986

This paper introduces novel functionally integrated logic elements which are conceptuallized for large scale integrated circuits. Efforts are made to minimize the gate size as well as to reduce the operational voltage, without sacrificing the speed performance of the gates. The process used was a rather conventional collector diffusion isolation(CDI) process. New gate structures are formed by merging several transistors of a gate in the silicon substrate. Thested elements are CML(Current Mode Logic) and EECL (Emitter-to-Emitter Coupled Logic)gates. The obtained experimental results are power-delay product of 6~11pJ and delay time/gate of 1.6~1.8 ns, confirming the possibility of these novel gate structures as a VLSI-candidate.

• Journal of Information Display
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• v.6 no.1
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• pp.17-21
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• 2005

We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE .simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.

• Korean Journal of Optics and Photonics
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• v.13 no.5
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• pp.414-420
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• 2002

We realized optical logic gates using a bacteriorhodopsin (bR) doped polymer film. The bR undergoes a complex photocycle characterized by several spectroscopically distinct intermediate states. We realized optical logic gates using a He-Ne laser (632.8 nm) and a He-Cd laser (413 nm) that consider B-state and absorption change of M-state in the photocycle of bR. Also, we realized high speed AND logic gate using He-Ne laser (632.8 nm) and the second harmonics at 532 nm from a pulsed Nd-YAG laser that considering absorption spectrum between B-state and K-state.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.