• Title/Summary/Keyword: Logic gates

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New Dynamic Logic Gate Design Method for Improved TFT Circuit Performance

  • Jeong, Ju-Young;Kim, Jae-Geun
    • Journal of Information Display
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    • v.6 no.1
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    • pp.17-21
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    • 2005
  • We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE .simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.

All Optical Logic Gates Based on Two Dimensional Plasmonic Waveguides with Nanodisk Resonators

  • Dolatabady, Alireza;Granpayeh, Nosrat
    • Journal of the Optical Society of Korea
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    • v.16 no.4
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    • pp.432-442
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    • 2012
  • In this paper, we propose, analyze and simulate the performances of some new plasmonic logic gates in two dimensional plasmonic waveguides with nanodisk resonators, using the numerical method of finite difference time domain (FDTD). These gates, including XOR, XNOR, NAND, and NOT, can provide the highly integrated optical logic circuits. Also, by cascading and combining these basic logic gates, any logic operation can be realized. These devices can be utilized significantly in optical processing and telecommunication devices.

A Design of a Ternary Storage Elements Using CMOS Ternary Logic Gates (CMOS 3치 논리 게이트를 이용한 3치 저장 소자 설계)

  • Yoon, Byoung-Hee;Byun, Gi-Young;Kim, Heung-Soo
    • Journal of IKEEE
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    • v.8 no.1 s.14
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    • pp.47-53
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    • 2004
  • We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are composed with ternary voltage mode NMAX, NMIN, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.35um CMOS technology and 3.3Volts supply voltage. The architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

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Study for Digital Logic Circuit Using Resonant Tunneling Diodes (공명투과다이오드를 이용한 논리회로의 응용 연구)

  • 추혜용;박평운;이창희;이일항
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.2
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    • pp.75-80
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    • 1994
  • AlAs/GaAs/AlAs RTDs(Resonant Tunneling Diodes) are fabricated and current-voltage properties of them are measured. At room temperature, peak to valley ratio is 2.4 NOT.AND.OR logic gates and Flip-Flop are fabricated using the bistable characteristics of RTDs. Although NOT.AND.OR logic gates need 5~8 transistors. only one RTD is sufficient to fabricate the logic gates. Since the switching time is very short(<10$^12$sec), it is possible to drive the semiconductor circuits fast and integrate them very large. And it is convinced the possibility of integrating RTDs to multilevel logic circuits by observing two peaks of similar current in the serial connection of two RTDs.

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Probability subtraction method for accurate quantification of seismic multi-unit probabilistic safety assessment

  • Park, Seong Kyu;Jung, Woo Sik
    • Nuclear Engineering and Technology
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    • v.53 no.4
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    • pp.1146-1156
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    • 2021
  • Single-unit probabilistic safety assessment (SUPSA) has complex Boolean logic equations for accident sequences. Multi-unit probabilistic safety assessment (MUPSA) model is developed by revising and combining SUPSA models in order to reflect plant state combinations (PSCs). These PSCs represent combinations of core damage and non-core damage states of nuclear power plants (NPPs). Since all these Boolean logic equations have complemented gates (not gates), it is not easy to generate exact Boolean solutions. Delete-term approximation method (DTAM) has been widely applied for generating approximate minimal cut sets (MCSs) from the complex Boolean logic equations with complemented gates. By applying DTAM, approximate conditional core damage probability (CCDP) has been calculated in SUPSA and MUPSA. It was found that CCDP calculated by DTAM was overestimated when complemented gates have non-rare events. Especially, the CCDP overestimation drastically increases if seismic SUPSA or MUPSA has complemented gates with many non-rare events. The objective of this study is to suggest a new quantification method named probability subtraction method (PSM) that replaces DTAM. The PSM calculates accurate CCDP even when SUPSA or MUPSA has complemented gates with many non-rare events. In this paper, the PSM is explained, and the accuracy of the PSM is validated by its applications to a few MUPSAs.

Circuit Design of a Ternary Flip-Flop Using Ternary Logic Gates

  • Kim, Jong-Heon;Hwang, Jong-Hak;Park, Seung-Young;Kim, Heung-Soo
    • Proceedings of the IEEK Conference
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    • 2000.07a
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    • pp.347-350
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    • 2000
  • We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

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Design Method of Current Mode Logic Gates for High Performance LTPS TFT Digital Circuits (LTPS TFT 논리회로 성능향상을 위한 전류모드 논리게이트의 설계 방법)

  • Lee, J.C.;Jeong, J.Y.
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.9
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    • pp.54-58
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    • 2007
  • Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

Design of FM sound synthesizer IC for multimedia with phase bit optimized (위상 데이터 비트수를 최적화한 멀티미디어용 FM 음원합성 IC의 설계)

  • 홍현석;김이섭
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.11
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    • pp.2978-2990
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    • 1996
  • With the advent of multimedia era, there are ever increasing interest in computer music and sound syntheis. An FM type sound synthesizing method makes possible the syntheis ofvarious sounds ofmusical instruments with a relatively simple hardware architecture. Therefore, in this paper, we designed a hardware architecture for real-time sound synthesizer and its logic gates. In this paper, we designed a basic sound generator for implementation of real-time logic gates, analzed characteristics of sounds synthesized in this architecture and extracted parameters of FM sounds of musical instruments by using the Csound software. The major bolkcs to build the hardware are a phase-generator, a singe-function-generator, an envelope-generator and a multiplier-part. Finally, logic circuits are designed and verified in VHDL and logic gates by 1.0um standard cell library, which will be easily implementable by the form of ASIC.

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Optical AND/OR gates based on monolithically integrated vertical cavity laser with depleted optical thyristor (집적화된 광 싸이리스터와 수직구조 레이저를 이용한 광 로직 AND/OR 게이트에 관한 연구)

  • Kim Doo-Gun;Jung In-Il;Choi Young-Wan;Choi Woon-Kyung
    • 한국정보통신설비학회:학술대회논문집
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    • 2006.08a
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    • pp.19-23
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    • 2006
  • Latching optical switches and optical logic gates AND and OR are demonstrated, for the first time, by the monolithic integration of a vertical cavity lasers with depleted optical thyristor structure, which have not only a low threshold current with 0.65 mA. but also a high on/off contrast ratio more than 50 dB. By simple operating technique with changing a reference switching voltage, this single device operates as two logic functions, optical logic AND and OR. The thyristor laser fabricated using the oxidation process achieved a high optical output power efficiency and a high sensitivity to the optical input light.

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Realization of optical logic gates using photocycle properties of bacteriorhodopsin (박테리아로돕신의 광순환 특성을 이용한 광학적 논리회로 구현)

  • 오세권;유연석
    • Korean Journal of Optics and Photonics
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    • v.13 no.5
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    • pp.414-420
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    • 2002
  • We realized optical logic gates using a bacteriorhodopsin (bR) doped polymer film. The bR undergoes a complex photocycle characterized by several spectroscopically distinct intermediate states. We realized optical logic gates using a He-Ne laser (632.8 nm) and a He-Cd laser (413 nm) that consider B-state and absorption change of M-state in the photocycle of bR. Also, we realized high speed AND logic gate using He-Ne laser (632.8 nm) and the second harmonics at 532 nm from a pulsed Nd-YAG laser that considering absorption spectrum between B-state and K-state.