• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.5
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• pp.270-277
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• 2000

A new Lateral Trench-MOS Bipolar-Mode Field-Effect Transistor(LTMBMFET) is proposed and verified by MEDICI simulation. By using a trench MOS structure, the proposed device can enhance the current gain without sacrificing other device characteristics such as the breakdown voltage. The channel region of the proposed device is formed between the trench MOS structure. So the effect of the substrate voltage is negligible when compared with the conventional device which has a channel region between the gate junction and the buried oxide layer.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.895-900
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• 1990

With the MOS device scailing down, the substrate concentration must increase in order to avoid punchthrough leakage current due to the DIBL(Drain Induced Barrier Lowering) effect. However the enhancement of the substrate concentration increases source, drain juntion capacitances and substrate current due to hot elelctron, degrading the speed characteristics and reliability of the MOS devices. In this paper, a new device, called CODE(Channel Only Dopant Enhancement) MOS, an its fabrication are proposed. By comparing the fabricated CODE MOSFET with the conventional device, the improvements on DIBL, substrate current and source, drain juntion capacitances are realized.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.301-305
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• 2009

Pt nanoparticles with a narrow size distribution (dia. ~4 nm) were synthesized via an alcohol reduction method and used for the fabrication of hybrid Pt-$SiO_2$ nanoparticles. Also, the self-assembled monolayer of Pt nanoparticles (NPs) was studied as a charge trapping layer for non-volatile memory (NVM) applications. A metal-oxide-semiconductor (MOS) type memory device with Pt NPs exhibits a relatively large memory window. These results indicate that the self-assembled Pt NPs can be utilized for NVM devices. In addition, it was tried to show the control of thin-film thickness of hybrid Pt-$SiO_2$ nanoparticles indicating the possibility of much applications for the MOS type memory devices.

• Journal of IKEEE
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• v.22 no.3
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• pp.706-711
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• 2018

In this work, we have investigated the characteristics of 4H-SiC metal-oxide-semiconductor (MOS) devices with silicon oxynitride (SiON) insulator using plasma enhanced chemical vapor deposition (PECVD). After post metallization annealing, the trap densities of the fabricated devices decreased significantly. In particular, the device annealed at $500^{\circ}C$ in forming gas ambient exhibited excellent MOS characteristics along with negligible hysteresis, which proved the potential of PECVD SiON as an alternative gate insulator for use in 4H-SiC MOS device.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.400-402
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• 1987

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.6
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• pp.2697-2701
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• 2012

The yield of OTP devices using anti-fuse MOS capacitor have been affected by the input resistance, the size of the pass transistor and the read transistor, and the readout voltage of programed cell. To investigate the element which gives an effect to yield, we analyze the full map data of the resistance characterization of OTP device and those data in a various experimental condition. As a result, we got the optimum conditions which is necessary to the yield improvement. The optimum conditions are as follows: Input resistance is 50 ohms, the channel length of pass transistor is 10um, read voltage is 2.8 volt, respectively.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.6
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• pp.203-211
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• 1984

MOS silicon solar cells have been developed using the fixed (interface) charge inherent to thermally oxidized silicon to induce an n-type inversion layer in 1-10 ohm-cm p-type silicon. Higher collection efficiencies are predicted than for diffused junction cells. Without special precautions a conversion efficiency of 14.2% is obtained. A MOS silicon solar cell is described in which an inversion layer forms the active area which is then contacted by means of a MOS grid. The highest efficiency is obtained when the resistivity of the substrate is high.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.9-12
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• 2004

In this paper, a new small sized Lateral Trench Electrode Power MOS was proposed. This new structure, called LTEMOS(Lateral Trench Electrode Power MOS), was based on the conventional lateral power MOS. But the entire electrodes of LTEMOS were placed in trench oxide. The forward blocking voltage of the proposed LTEMOS was improved by 1.5 times with that of the conventional lateral power MOS. The forward blocking voltage of LTEMOS was about 240 V. At the same size, an improvement of the forward blocking voltage of about 1.5 times relative to the conventional MOS was observed by using ISE-TCAD which was used for analyzing device's electrical characteristics. Because all of the electrodes of the proposed device were formed in each trench oxide, the electric field was crowded to trench oxide and punch-through breakdown was occurred, lately.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.351-354
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• 2004

This thesis presents Bipolar transistor with SAVEN(Self-Aligned VErtical Nitride) structure as a high-speed device which is essential for high-speed system such as optical storage system or mobile communication system, and proposes 0.8${\mu}m$ BiCMOS Process which integrates LDD nMOS, LDD pMOS and SAVEN bipolar transistor into one-chip. The SPICE parameters of LDD nMOS, LDD pMOS and SAVEN Bipolar transistor are extracted, and comparator operating at 500MHz sampling frequency is designed with them. The small Parasitic capacitances of SAVEN bipolar transistor have a direct effect on decreasing recovery time and regeneration time, which is helpful to improve the speed of the comparator. Therefore the SAVEN bipolar transistor with high cutoff frequency is expected to be used in high-speed system.

• Transactions on Electrical and Electronic Materials
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• v.6 no.1
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• pp.1-5
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• 2005

Continued scaling of MOS devices requires the formation of the ultra shallow and very heavily doped junction. The simulation and experiment results show that the degradation of pMOS performance in logic and SRAM pMOS devices due to the excessive diffusion of the tail and a large amount of dose loss in the extension region. This problem comes from the high-temperature long-time deposition process for forming the spacer and the presence of fluorine which diffuses quickly to the $Si/SiO_{2}$ interface with boron pairing. We have studied the method to improve the pMOS performance that includes the low-energy boron implantation, spike annealing and device structure design using TCAD simulation.