• Computers and Concrete
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• v.23 no.5
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• pp.311-320
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• 2019

The substructuring technique is one of the efficient methods for reducing computational effort and memory usage in the finite element method, especially in large-scale structures. Proper mesh partitioning plays a key role in the efficiency of the technique. In this study, new algorithms are proposed for mesh partitioning based on an element search technique. The computational cost function is optimized by aligning each element of the structure to a proper substructure. The genetic algorithm is employed to minimize the boundary nodes of the substructures. Since the boundary nodes have a vital performance on the mesh partitioning, different strategies are proposed for the few number of substructures and higher number ones. The mesh partitioning is optimized considering both computational and memory requirements. The efficiency and robustness of the proposed algorithms is demonstrated in numerous examples for different size of substructures.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.808-816
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• 2016

As the number of CPU/GPU cores and IPs in SOC increases and applications require explosive memory bandwidth, simultaneously achieving good throughput and fairness in the memory system among interfering applications is very challenging. Recent works proposed priority-based thread scheduling and channel partitioning to improve throughput and fairness. However, combining these different approaches leads to performance and fairness degradation. In this paper, we analyze the problems incurred when combining priority-based scheduling and channel partitioning and propose dynamic priority thread scheduling and adaptive channel partitioning method. In addition, we propose dynamic address mapping to further optimize the proposed scheme. Combining proposed methods could enhance weighted speedup and fairness for memory intensive applications by 4.2% and 10.2% over TCM or by 19.7% and 19.9% over FR-FCFS on average whereas the proposed scheme requires space less than TCM by 8%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.105-113
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• 2004

This paper presents a design method for an asynchronous memory with a completion signal generation circuit meeting D-I model. The proposed design method is to generates a completion signal with dummy cell and a completion signal generation circuit to indicate completion of the required read or write operation to the processor. Dividing a memory exponentially to consider delay of a bit-line and a memory cell makes memory operates as a D-I model with minimum addition of redundant circuit. The proposed memory partitioning algorithm that divides entire memory into the several partitions with a exponentially increased size reduces the memory access delay by 40% compared with a conventional partitioning method to the same size.

• Journal of Computing Science and Engineering
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• v.4 no.3
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• pp.207-224
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• 2010

This paper presents a compression scheme for mesh geometry, which is suitable for mobile graphics. The main focus is to enable real-time decoding of compressed vertex positions while providing reasonable compression ratios. Our scheme is based on local quantization of vertex positions with mesh partitioning. To prevent visual seams along the partitioning boundaries, we constrain the locally quantized cells of all mesh partitions to have the same size and aligned local axes. We propose a mesh partitioning algorithm to minimize the size of locally quantized cells, which relates to the distortion of a restored mesh. Vertex coordinates are stored in main memory and transmitted to graphics hardware for rendering in the quantized form, saving memory space and system bus bandwidth. Decoding operation is combined with model geometry transformation, and the only overhead to restore vertex positions is one matrix multiplication for each mesh partition. In our experiments, a 32-bit floating point vertex coordinate is quantized into an 8-bit integer, which is the smallest data size supported in a mobile graphics library. With this setting, the distortions of the restored meshes are comparable to 11-bit global quantization of vertex coordinates. We also apply the proposed approach to compression of vertex attributes, such as vertex normals and texture coordinates, and show that gains similar to vertex geometry can be obtained through local quantization with mesh partitioning.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8A
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• pp.814-821
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• 2002

The SPIHT(set partitioning in hierarchical tree) is efficient and well-known in the zerotree coding algorithm. However SPIHT's high memory requirement is a major difficulty for hardware implementation. In this paper we propose low-memory and fast zerotree algorithm. We present following three methods for reduced memory and fst coding speed. First, wavelet transform by lifting has a low memory requirement and reduced complexity than traditional filter bank implementation. The second method is to divide the wavelet coefficients into a block. Finally, we use NLS algorithm proposed by Wheeler and Pearlman in our codec. Performance of NLS is nearly same as SPIHT and reveals low and fixed memory and fast coding speed.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.3
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• pp.487-499
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• 2022

Machine learning such as deep learning have been widely used in recent years. Recently deep learning is performed in a trusted execution environment such as ARM TrustZone to improve security in edge devices and embedded devices with low computing resource. To mitigate this problem, we propose TPMP that efficiently uses the limited memory of TEE through DNN model partitioning. TPMP achieves high confidentiality of DNN by performing DNN models that could not be run with existing memory scheduling methods in TEE through optimized memory scheduling. TPMP required a similar amount of computational resources to previous methodologies.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.5
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• pp.1-10
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• 1998

In this paper, a new hardware-software patitioning algorithm is presented, in which the system behavioral description containing a mixture of hardware and softwae components is partitioned into the hardware part and the software part. In this research, new techniques to optimally partition a mixed system under certain specified constaints such as performance, area, and delay, have been developed. During the partitioning process, the overhead due to the communication between the hardware and software parts are considered. New featues have been added to adjust the hierarchical level of partitioning. Power consumption, memory cost, and the effect of pipelining can also be considered during partitioning. Another new feature is the ability to partition a DSP system under throughput constraints. This feature is important for real time processing. The developed partitioning system can also be used to evaluate various design alternatives and architectures.

• Journal of Korean Institute of Industrial Engineers
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• v.24 no.4
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• pp.661-671
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• 1998

It is important to minimize the number of disk accesses which is necessary to transfer data in disk into main memory when processing transactions in physical database design. A vertical file partitioning method is used to reduce the number of disk accesses by partitioning relations vertically and accessing only necessay fragments. In this paper, SOFM(Self-Organizing Feature Maps) network is used to solve vertical partitioning problems. This paper shows that SOFM network is efficient in solving vertical partitioning problem by comparing approximate solution of SOFM network with optimal solution of N-ary branch and bound method. And this paper presents a heuristic algorithm for allocating duplicate attributes to vertically partitioned fragments. As branch and bound method requires particularly much computing time to solve large-sized problems, it is shown that SOFM network is able to overcome this limitation of branch and bound method and solve large-sized problems efficiently in a short time.

• Journal of Korea Multimedia Society
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• v.10 no.11
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• pp.1516-1522
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• 2007

We had proposed the FPA(Fixed Partition Averaging) method in order to improve the storage requirement and classification rate of the Memory Based Reasoning. The algorithm worked not bad in many area, but it lead to some overhead for memory usage and lengthy computation in the multi classes area. We propose an Repetitive FPA algorithm which repetitively partitioning pattern space in the multi classes area. Our proposed methods have been successfully shown to exhibit comparable performance to k-NN with a lot less number of patterns and better result than EACH system which implements the NGE theory.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.19 no.37
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• pp.241-249
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• 1996

In this paper, a 0-1 integer programming model for solving vertical partitioning problem minimizing the number of disk accesses is formulated and a branch-and-bound method is used to solve the binary vertical partitioning problem. In relational databases, the number of disk accesses depends on the amount of data transferred from disk to main memory for processing the transactions. Vertical partitioning of the relation can often result in a decrease in the number of disk accesses, since not all attributes in a tuple are required by each transactions. The algorithm is illustrated with numerical examples and is shown to be computationally efficient. Numerical experiments reveal that the proposed method is more effective in reducing access costs than the existing algorithms.