• 한국정보통신학회논문지
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• 제26권5호
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• pp.682-687
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• 2022

터널링 전계효과 트랜지스터(tunneling field-effect transistor; TFET)로 적층된 3차원 적층형 집적회로(monolithic 3D integrated-circuit; M3DIC)에 대한 연구 결과를 소개한다. TFET는 MOSFET(metal-oxide-semiconductor field-effect transistor)와 달리 소스와 드레인이 비대칭 구조이므로 대칭구조인 MOSFET의 레이아웃과 다르게 설계된다. 비대칭 구조로 인해서 다양한 인버터 구조 및 레이아웃이 가능하고, 그 중에서 최소 금속선 레이어를 가지는 단순한 인버터 구조를 제안한다. 비대칭 구조의 TFET를 순차적으로 적층한 논리 게이트인 NAND 게이트, NOR 게이트 등의 M3DIC의 구조와 레이아웃을 제안된 인버터 구조를 바탕으로 제안한다. 소자와 회로 시뮬레이터를 이용해서 제안된 M3D 논리게이트의 전압전달특성 결과를 조사하고 각 논리 게이트의 동작을 검증한다. M3D 논리 게이트 별 셀 면적은 2차원 평면의 논리게이트에 비해서 약 50% 감소된다.

• Journal of information and communication convergence engineering
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• 제20권2호
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• pp.137-142
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• 2022

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

• ETRI Journal
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• 제33권5호
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• pp.818-821
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• 2011

A D-band subharmonically-pumped resistive mixer has been designed, processed, and experimentally tested. The circuit is based on a $180^{\circ}$ power divider structure consisting of a Lange coupler followed by a ${\lambda}$/4 transmission line (at local oscillator (LO) frequency). This monolithic microwave integrated circuit (MMIC) has been realized in coplanar waveguide technology by using an InAlAs/InGaAs-based metamorphic high electron mobility transistor process with 100-nm gate length. The MMIC achieves a measured conversion loss between 12.5 dB and 16 dB in the radio frequency bandwidth from 120 GHz to 150 GHz with 4-dBm LO drive and an intermediate frequency of 100 MHz. The input 1-dB compression point and IIP3 were simulated to be 2 dBm and 13 dBm, respectively.

• Journal of Advanced Marine Engineering and Technology
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• 제37권1호
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• pp.99-104
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• 2013

본 논문에서는 밀리미터파에의 응용을 위하여, 소형화된 다운컨버터 MMIC(monolithic microwave integrated circuit)를 제안하였다. 구체적으로는, RF(radio frequency) 및 LO(local oscilator) 신호의 격리특성을 위해 Lange 커플러가 삽입되었고, ${\lambda}$/4 전송선로를 연결하여 역위상 RF와 동위상 LO 신호가 믹서부분 FET(field effect transistor)의 게이트에 인가되었다. 또한, IF(intermediate frequency) 출력 신호의 역위상의 결합과 LO 누설신호 제거를 위하여 역위상 결합용 능동 벌룬이 출력 포트에 설치되었다. 측정 결과에 따르면, 제안된 다운컨버터 MMIC는 양호한 RF 특성을 보였다. 구체적으로, 63 GHz의 RF 주파수와 60.6 GHz의 LO 주파수에서 IF 출력 포트에서의 LO 누설 전력이 .25 dBc, RF와 LO의 격리특성은 18 dB를 보였으며, 변환 이득이 10.3 dB를 보였다. 따라서, SAW 필터와 같은 LO 제거용 off-chip 소자는 제안된 다운컨버터 MMIC에서는 필요하지 않게 되었다. 모든 능동소자와 수동소자가 GaAs MMIC 내부에 집적되었으며, 전체 사이즈는 $2.2{\times}1.4mm^2$ 로써 초소형 MMIC가 구현되었다.

• ETRI Journal
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• 제35권3호
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• pp.546-549
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• 2013

A Ka-band 6-W high power microwave monolithic integrated circuit amplifier for use in a very small aperture terminal system requiring high linearity is designed and fabricated using commercial 0.15-${\mu}m$ GaAs pHEMT technology. This three-stage amplifier, with a chip size of 22.1 $mm^2$ can achieve a saturated output power of 6 W with a 21% power-added efficiency and 15-dB small signal gain over a frequency range of 28.5 GHz to 30.5 GHz. To obtain high linearity, the amplifier employs a class-A bias and demonstrates an output third-order intercept point of greater than 43.5 dBm over the above-mentioned frequency range.

• 한국ITS학회 논문지
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• 제2권2호
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• pp.97-101
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• 2003

본 논문에서는 Ku-band용 주파수 하향변환기에 사용할 수 있는 MMIC (monolithic microwave integrated circuit) mixer를 InGaAs/GaAs p-HEMT 공정의 Schottky diode를 이용하여 설계 및 제작하였다. 일반적인 double balanced mixer의 구조에서 IF단자와 LO 단자를 서로 바꾸어 설계함으로써 mC chip의 크기를 크게 줄일 수 있었다. 설계된 MMIC mixer는 RF(14.0 - 14.5 GHz)와 IF(12.252 - 12.752 GHz)의 주파수 대역에서 사용할 수 있다. 제작된 초소형의 MMIC mixer chip은 크기가 3.3 m X 3.0 m이고, on-wafer측정 결과 9.8 dB 이하의 변환손실과 23 dB 이상의 RF-to-IF 격리도 및 38 dB 이상의 LO-to-IF 격리도의 특성을 각각 얻었다.

• ETRI Journal
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• 제36권3호
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• pp.498-501
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• 2014

A C-band 50 W high-power microwave monolithic integrated circuit amplifier for use in a phased-array radar system was designed and fabricated using commercial $0.25{\mu}m$ AlGaN/GaN technology. This two-stage amplifier can achieve a saturated output power of 50 W with higher than 35% power-added efficiency and 22 dB small-signal gain over a frequency range of 5.5 GHz to 6.2 GHz. With a compact $14.82mm^2$ chip area, an output power density of $3.2W/mm^2$ is demonstrated.

• ETRI Journal
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• 제25권1호
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• pp.19-24
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• 2003

This paper describes the performance of a Ku-band 5-bit monolithic phase shifter with metal semiconductor field effect transistor (MESFET) switches and the implementation of a ceramic packaged phase shifter for phase array antennas. Using compensation resistors reduced the insertion loss variation of the phase shifter. Measurement of the 5-bit phase shifter with a monolithic microwave integrated circuit demonstrated a phase error of less than $7.5{\circ}$ root-mean-square (RMS) and an insertion loss variation of less than 0.9 dB RMS for 13 to 15 GHz. For all 32 states of the developed 5-bit phase shifter, the insertion losses were $8.2{\pm}1.4$dB, the input return losses were higher than 7.7 dB, and the output return losses were higher than 6.8 dB for 13 to 15 GHz. The chip size of the 5- bit monolithic phase shifter with a digital circuit for controlling all five bits was 2.35 mm ${\times}$1.65 mm. The packaged phase shifter demonstrated a phase error of less than $11.3{\circ}$ RMS, measured insertion losses of 12.2 ${\pm}$2.2 dB, and an insertion loss variation of 1.0 dB RMS for 13 to 15 GHz. For all 32 states, the input return losses were higher than 5.0 dB and the output return losses were higher than 6.2 dB for 13 to 15 GHz. The size of the packaged phase shifter was 7.20 mm${\times}$ 6.20 mm.

• ETRI Journal
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• 제9권3호
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• pp.127-138
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• 1987

본고에서는 MMIC (Monolithic Microwave Integrated Circuit)의 연구동향을 미국을 중심으로 소개한다. MMIC의 역사, 공정, 소자, 설계, packaging, 측정에 대하여 조사함으로써 차세대 화합물반도체 MMIC개발의 앞으로의 방향을 모색하고자 한다. 본고는 미국 Microwave & RF 논문지 1987년 3월호에 게재된 R. S. Pegally와 D. Maki의 논문내용을 중심으로 편역한 것이다.

• Journal of information and communication convergence engineering
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• 제14권1호
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• pp.40-44
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• 2016

The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness T_ILD and dielectric constant ε_r of the inter-layer distance (ILD), the doping concentration N_d (N_a), and length L_g of the channel, and the side-wall length L_SW where the stacked FETs are coupled are studied. When N_d (N_a) < 10¹⁶ cm^-3 and L_SW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when N_d (N_a) > 10¹⁶ cm^-3 or L_SW > 20 nm, the shift decreases and increases, respectively. M3INVs with T_ILD ≥ 50 nm and ε_r ≤ 3.9 can neglect the interaction between the stacked FETs, but when T_ILD or ε_r do not meet the above conditions, the interaction must be taken into consideration.