• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.319-320
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• 2006

In order to improve the ESD(Electrical Static Discharge) resistance of multilayer chip varistors, we have investigated ZnO-$Pr_6O_{11}$ based chip varistor by applying tape casting technology, whose fundamental component were ZnO : $Pr_6O_{11}$ :$Co_3O_4$: $Y_2O_3$: $Al_2O_3$=93.67: 2.53:2.53:1.25 : 0.015 (wt %). The effect of sintering condition on the multilayer chip varistors and electric properties was studied. The electrical properties and ESD resistance of multilayer chip varistor could be influenced the sintering temperature and condition.

• Journal of the Korean Ceramic Society
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• v.35 no.11
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• pp.1121-1129
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• 1998

Reactions between Ag-Pd internal electrode materials and{{{{ { {Bi }_{2 }O }_{3 } }} in multilayer chip varistor were in-vestigated. For more than 1 mol%{{{{ { {Bi }_{2 }O }_{3 } }} in varistor composition internal electrode structure was destroyed due to the reaction between internal electrode and{{{{ { {Bi }_{2 }O }_{3 } }} But for typical varistor compositions (below 1 mol% of{{{{ { {Bi }_{2 }O }_{3 } }} content) microstructural changes around the internal electrode were not observed. However SEM-EDS and TEM-EDS analysis showed the uneven distribution of{{{{ { {Bi }_{2 }O }_{3 } }} in the internal electrode which was due to the migration of{{{{ { {Bi }_{2 }O }_{3 } }} to the electorde during sintering. As a results the nonlinear coefficient of multilayer varistor showed very large distribution as well as the breakdown voltage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.6
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• pp.496-501
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• 2007

In order to enhance sintering characteristics on the $ZnO-Pr_6O_{11}$ based multilayer chip varistors (MLVs), a response surface analysis using central composite design method were carried out. As a result, varistor voltage($V_{1mA}$), nonlinear coefficient ($\alpha$), leakage current ($I_L$) and capacitance (C) were considered to be mainly affected by sintered temperature and holding time. MLVs sintered at $1200^{\circ}C$ and above $1200^{\circ}C$ revealed poor electrical characteristics, possibly due to the reaction between electrode materials(Pd) and $ZnO-Pr_6O_{11}$ based ceramics. On the sintering temperature range $1150{\sim}1175^{\circ}C$, nonlinear coefficient ($\alpha$) and leakage current ($I_L$) were shown to be $60{\sim}69$ and below $0.3{\mu}A$, respectively. In particular, MLVs sintered at $1175^{\circ}C$, 1.5 hr and $2^{\circ}C/hr$ (cooling speed) showed stable ESD(Electrical Static Discharge) characteristics under the condition of 10 times at 8 Kv with deviation varistor voltage, and deviation nonlinear coefficient were 0.3% and 0.33% (at positive), 0.55% (at negative), respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.876-881
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• 2011

The sintering, defect and grain boundary characteristics of Bi-based ZnO chip varistor (1,608 mm size) have been investigated to know the possibility of lowering a manufacturing price by using 100 % Ag inner-electrode. The samples were prepared by general multilayer chip varistor process and characterized by shrinkage, SEM, current-voltage (I-V), admittance spectroscopy (AS), impedance and modulus spectroscopy (IS & MS) measurement. There are no problems to make a chip varistor with 100% Ag inner-electrode in the sintering temperature range of 850~900$^{\circ}C$ for 1 h in air. A good varistor characteristics ($V_n$= 9.3~15.4 V, a= 23~24, $I_L$= 1.0~1.6 ${\mu}A$) were revealed but formed $Zn_i^{{\cdot}{\cdot}}$(0.209 eV) as dominant defect, and increased the distributional inhomogeneity and the temperature instability in grain boundary barriers.

• The Korean Journal of Ceramics
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• v.5 no.4
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• pp.357-362
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• 1999

ZnO varistors containing cobalt, praseodymium and calcium oxides were prepared. The current-voltage charcteristics and microstructures of the specimens were investigated with respect to calcium addition and sintering temperature. The potential barrier heights and the carrier densities were estimated from C-V relations. The compatibility of Ag-Pd as an internal electrode for multilayer chip varistor was also examined.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.244-245
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• 2007

본 논문은 적층 칩 바리스터의 외부단자 도금을 할 때 세라믹 표면에 절연성을 부여하기 위해 glass coating할 때 열처리 회수에 따른 전기적 특성을 연구하였다. 열처리 횟수의 증가에 따라 바리스터 전압의 변화는 크게 나타나지는 않으나 신리성에 영향을 미치는 누설전류 및 비직선계수는 열화되는 현상을 보이지만 glass coating을 통하여 전기 도금시 칩 바리스터 표면이 도금되지 않고 생산 할 수 있음을 확인하였다.