• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.3
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• pp.27-36
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• 2012

With the increase of various user's requirements, lots of interesting applications on the Internet have been emerging recently. However, Internet has many limitations for providing upcoming new services because it was only designed to provide basic connectivity between research networks and simplified forwarding functions at the first time. Internet has many problems in the aspects of routing scalability, mobility, security and QoS, so lots of researches are being actively performed in many countries to solve these problems. In this paper, we implement RED(Random Early Detection) scheduler using NetFPGA platform and local testbed to provide active queue management. Using the implemented RED scheduler, packets are dropped according to the specified drop probability, so Global Synchronization coming from simultaneous TCP segment losses in a congestion condition can be prevented. With the comparison to the Drop-Tail scheme in the basic router, we show TCP performance can be enhanced in the congestion situation using the NetFPGA-based RED scheduler.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.7
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• pp.118-127
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• 2010

Current TCP/IP-based Internet architecture has been used for over 30 years, however it will confront with fundamental problems due to new protocol extension limitation since communication environments will change drastically and various user requirements will be emerging in near future. To solve these problems, major countries have started Future Internet researches based on clean slate approach and they will deploy large-scale testbed to experiment and verify new functions. OpenFlow switch technology has been proposed as a new experimental technology for independent protocol that can utilized the legacy network devices and does not interfere with the production Internet traffic. Korea also started Future Internet testbed project called FIRST and OpenFlow switch with NetFPGA card will be used to deploy this testbed. To interconnect distributed testbed using OpenFlow switches, logical tunnel should be established by encapsulating MAC frame inside a unicast IP packet between OpenFlow switches because OpenFlow switches are not directly connected. In this paper, we have implemented a NetFPGA-based that performs MAC in IP tunneling between various OpenFlow switch sites implemented in domestic research network KOREN. The performance evaluation shows that the NetFPGA-based capsulator reveals better performance than the software-based tunneling and it can be utilized as a testbed for experimentation of Future Internet technologies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.9-17
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• 2012

High-quality multimedia on the Internet has attracted attention because of its wide application area. IP multicast has been proposed as a solution to use efficient network resources in these services. However, IP multicast has not been commonly used due to a number of practical issues such as security and management. As an alternative, an overlay multicast routing which is performed in upper protocol layers on legacy networks without changing hardware has been presented. Yet, the maximum data transmission capacity of the overlay multicast is not sufficient for real time transmission of multimedia data. In this paper, we have implemented an overlay multicast engine on NetFPGA which allows us to perform packet replication and tunneling which need high-speed. In addition, we have implemented extra portions which need low-speed in software. From now on, we will progress research which increase the number of terminal spots which can be replicated by improvement and amplify throughputs by optimization.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.971-974
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• 2011

본 논문에서는 대용량 네트워크에 비정상적인 트래픽이 유입이 되거나 나가는 경우 패킷 기반의 비정상 트래픽의 탐지와 분석이 가능토록 하는 시스템을 설계하고 구현하였다. 본 논문에서 구현한 시스템은 네트워크상의 이상 행위를 탐지하기 위하여, DDoS HTTP Get Flooding 공격 탐지 알고리즘을 적용하고, NetFPGA를 이용하여 라우터 단에서 패킷을 모니터링하며 공격을 탐지한다. 본 논문에서 구현한 시스템은 Incomplete Get 공격 타입의 Slowloris 봇과, Attack Type-2 공격 타입의 BlackEnergy, Netbot Vip5.4 봇에 높은 탐지율을 보였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.1-8
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• 2018

Recently, the convolutional neural network shows high performance in many computer vision tasks. However, convolutional neural networks require enormous amount of operation, so it is difficult to adopt them in the embedded environments. To solve this problem, many studies are performed on the ASIC or FPGA implementation, where an efficient representation method is required. The fixed-point representation is adequate for the ASIC or FPGA implementation but causes a performance degradation. This paper proposes a separate optimization of representations for the convolutional layers and the batch normalization layers. With the proposed method, the required bit width for the convolutional layers is reduced from 16 bits to 10 bits for the ResNet-50 neural network. Since the computation amount of the convolutional layers occupies the most of the entire computation, the bit width reduction in the convolutional layers enables the efficient implementation of the convolutional neural networks.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.142-151
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• 1996

This paper presents a new symmetrical routing architecture for FPGA and an efficient routing algorithm for the architecture. The routing architecture adopts the segmented wires and the improved switch modules. Segmetned wires construct routing channels which pass through the chip in vertical and horizontal directions. To maximize the utility of a track, a track in each switch module can be separated in two part using a programmable switch to route two different net. The proposed routing algorithm finds all assignable tracks for a given net and selects the best track from assignable tracks to minimize the number of programmable switches and the unused portion of the wire segments. In order to stabilize the perfomrance of the algorithm, the routing order is defined by weighted sum of the number of wire segment, the length of wire segmetn, and the number of pin. Experimental results show that routability is improved dramatically and the number of crossing switches are reduced about 40% compared with the previous works.

• The KIPS Transactions:PartC
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• v.18C no.6
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• pp.413-422
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• 2011

Overlay network is a ready-to-use solution to enable new network functionality with existing Internet connectivity intact. This paper introduces a network service which helps users easily compose their own service overlay networks through software-defined networks. We look into the structure of service gateway which enables 1 Gbps packet processing on composed overlay networks. We also provide examples for the way of composing service overlay for support multicast applications. Experiment results carried over the KREONET (Korea Research Environment Open NETwork) show the forwarding performance of the service gateway.

• Nuclear Engineering and Technology
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• v.48 no.5
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• pp.1192-1205
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• 2016

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the "IEEE 1164 standard," registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.8
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• pp.42-50
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• 2011

Recently, research activities on the future internet are being actively performed in foreign and domestic. In domestic, ETRI and 4 universities are focused on implementation of a testbed for research on the future internet named as 'FiRST(Future Internet Research for Sustainable Testbed)'. In the 'FiRST' project, 4 universities are performing a project in collaboration named as 'FiRST@PC' project that is for an implementation of the testbed using the programmable platform-based openflow switches. Currently, the research on the virtualization of the testbed is being performed that has a purpose for supporting an isolated network to individual researcher. In this paper, we implemented a traffic scheduler for providing QoS by using the programmable platform that performs a hardware-based packet processing and we are implemented a testbed using that traffic scheduler. We perform a performance evaluation of the traffic scheduler on the testbed. As a result, we show that the hardware-based NetFPGA scheduler can provide reliable and stable QoS to virtualized networks of the Future Internet Testbed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.9
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• pp.35-46
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• 2011

Future Internet should support more efficient mobility management, flexible traffic engineering and various emerging new services. So, lots of traffic engineering techniques have been suggested and developed, but it's impossible to apply them on the current running commercial Internet. To overcome this problem, OpenFlow protocol was proposed as a technique to control network equipments using network controller with various networking applications. It is a software defined network, so researchers can verify their own traffic engineering techniques by applying them on the controller. In addition, for high-speed packet processing in the OpenFlow network, programmable NetFPGA card with four 1G-interfaces and commercial Procurve OpenFlow switches can be used. In this paper, we implement an OpenFlow test-bed using hardware-accelerated NetFPGA cards and Procurve switches on the KREONET, and implement CSPF (Constraint-based Shortest Path First) algorithm, which is one of popular QoS routing algorithms, and apply it on the large-scale testbed to verify performance and efficiency of multimedia traffic engineering scheme in Future Internet.