• Title/Summary/Keyword: One-Gate

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A Study on Gate driver with Boot-strap chain to Drive Multi-level PDP Driver Application (Multi-level PDP 구동회로를 위한 Gate driver의 Boot-strap chain에 관한 연구)

  • Nam, Won-Seok;Hong, Sung-Soo;SaKong, Suk-Chin;Roh, Chung-Wook
    • The Transactions of the Korean Institute of Power Electronics
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    • v.11 no.2
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    • pp.120-126
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    • 2006
  • A gate driver with Boot-strap chain is proposed to drive Multi-level PDP sustain switches. The proposed gate driver uses only one boot-strap capacitor and one diode per each MOSFETs switch without floating power supply. By adoption of this gate driver circuits, the size, weight and the cost of the driver board can be reduced.

Design of the Sequentially Operated-Hydraulic Cylinders Type Sluice Gate Minimizing the Operating Force (작동력을 최소화시키는 순차작동-유압실린더식 수문의 설계)

  • Lee, Seong-Rae
    • Proceedings of the KSME Conference
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    • 2004.11a
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    • pp.893-898
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    • 2004
  • The hydraulic cylinder is used for actuating a sluice gate which controls the volume of water in the reservoir. Generally, the one cylinder type is used to operate the sluice gate. In order to reduce the required cylinder force to operate the sluice gate significantly, the sequentially operated-hydraulic cylinders type is designed and the optimal locating points of cylinders are searched using the complex method that is one kind of constrained direct search method.

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Dynamic Characteristic of Lift Gate Supported by Plane Truss (평면트러스로 지지된 리프트 게이트의 진동특성)

  • Lee, Seong-Haeng;Yang, Dong-Woon;Hahm, Hyung-Gil;Kong, Bo-Sung;Shin, Dong-Wook
    • Journal of The Korean Society of Agricultural Engineers
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    • v.54 no.3
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    • pp.133-139
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    • 2012
  • Dynamic characteristic of lift gate supported by plane truss is studied by a model test scaled with the ratio of 1 : 31.25 in the four major rivers project. The vibrations of gate supported by the plane truss is assessed in comparison with those of gate supported by the space truss which was tested formerly. The gate model is made of acryl panel and calibrated by lead. A model test is conducted under the different gate opening and upstream water levels conditions in the concrete test flume dimensioned 1.6 m in width, 0.8 m in height and 24 m in length. In order to verify the model, natural frequencies of the model gate are measured, and compared with the numerical results. The vibrations of gate model supported by the plane truss in opening height of 1.0 cm~2.0 cm shows greater than one supported by the space truss. It is found that the gate model supported by the plane truss is less desirable than one supported by the space truss. thus, the latter type of gate model is requested to design.

Gate Location Design of an Automobile Junction Box with Integral Hinges (복합힌지를 갖는 차량용 정션박스의 게이트 위치설계)

  • 김홍석
    • Transactions of Materials Processing
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    • v.12 no.2
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    • pp.134-140
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    • 2003
  • Polymers such as polypropylene or polyethylene offer a unique feature of producing an integral hinge, which can flex over a million times without causing a failure. With such advantage manufacturing, time and cost required at the assembly stage can be eliminated by injecting the whole part as one piece. However, due to increased fluidity resistance at hinges during molding, several defects such as short shot or premature hinge failure can occur with the improper selection of gate locations. Therefore, it is necessary to optimize flow balancer in injection molding of part with hinges before actually producing molds. In this paper, resin flow patterns depending on several gate positions were investigated by numerical analyses of a simple strip part with a hinge. As a result, we found that the properly determined gate location leads to better resin flow and shorter hesitation time. Finally, injection molding tryouts using a mold that was designed one of the proposed gate systems were conducted using polypropylene that contained 20% talc. The experiment showed that hinges without defects could be produced by using the designed gate location.

Electrical Characteristics of Self Aligned Gate GaAs MESFETs Using Ion Beam Deposited Tungsten (이온빔 증착 텅스텐을 이용한 자기정렬 게이트 GaAs MESFET의 전기적 특성)

  • 편광의;박형무;김봉렬
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.12
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    • pp.1841-1851
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    • 1990
  • Self-aligned gate GaAs MESFETs using ion beam deposited tungsten applicable to GaAs LSI fabrication process have been fabricated. Silicon implanted samples were annealed using isothermla two step RTA process and conventional one step RTA process. The electrical and physicla characteristics of annealed samples were investigated using Hall and I-V measurements. As results of measurements, activation characteristics of the isothermal two step RTA process are better than those of one step annealed ones. Using the developed processes, GaAs SAFETs (Self-Aligned Gate FET) have been fabricated and electdrical characteirstics are measured. As results, subthreshold currents of SAGFETs are 6x10**-10 A/\ulcorner, that is compatible to conventional MESFET, maximum transconductances of 0.75\ulcorner gate MESFET using one step RTA process and 2\ulcorner gate MESFET using isothermal two step RTA process are 18 mS/mm, 41 mS/mm respectively.

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A Study on Application of Stepwise Gate Signal for a-Si Gate Driver (a-Si Gate 구동회로의 Stepwise Gate 신호적용에 대한 연구)

  • Myung, Jae-Hoon;Kwag, Jin-Oh;Yi, Jun-Sin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.21 no.3
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    • pp.272-278
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    • 2008
  • This paper investigated the a-si:H gate driver with the stepwise gate signal. In 1-chip type mobile LCD application the stepwise gate signal for low power consumption can be used by adding simple switching circuit. The power consumption of the a-Si:H gate driver can be decreased by employing the stepwise gate signal in the conventional circuit. In conventional one, the effect of stepwise gate signal can decrease slew rate and increase the fluctuation of gate-off state voltage, In order to increase the slew rate and decrease the gate off state fluctuation, we proposed a new a-Si:H TFT gate driver circuit. The simulation data of the new circuit show that the slew rate and the gate-off state fluctuation are improved, so the circuit can work reliably.

A Gi-point in Taoists and the conception of Life Gate in Korean medicine (도가(道家)의 기혈(氣穴)과 한의학(韓醫學)의 명문사상(命門思想))

  • Jeon, Hark-Soo;Noh, Young-Kyun
    • Journal of the Korean Institute of Oriental Medical Informatics
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    • v.14 no.2
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    • pp.47-57
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    • 2008
  • This paper aims at the comparative study of practicing Buddhism and Taoism related to "life gate". The term "life gate", as a physiological entity of disputed morphological identity, first appears in The Inner Canon where it refers to the eyes. Reference to a "life gate" as an internal organ body first appears in The Classic of Difficult Issues which states, "The two kidneys are not both kidneys' The left one is the kidney, and the right is the life gate." Successive scholars refers to life gate as a gi point of Taoists.. The question of the life gate invited little discussion until the Myeong and Cheong Dynasty, when various different theories were put forward. Especially Jin Sa-taek says "life gate" is the governor of the twelve place in the human body, throwing light on the meaning of it. Not that life gate denotes a local point, it does a system of life gate. Generally speaking, life gate designates cinnabar field. I think that the human body produces essence by way of life gate. That is, the human body is unified by the system of life gate. Life gate is not only the source of infusing the engine of the human body with vital energy but also as well as gi-point.

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A study on gate driver with Boot-strap chain to drive Multi-level PDP driver application (Multi-level을 사용한 PDP 구동회로를 위한 Gate driver 의 Boot-strap chain 에 관한 연구)

  • Nam, Won-Seok;Kim, Jun-Hyoung;Song, Suk-Ho;Roh, Chung-Wook;Hong, Sung-Soo;SaKong, Suk-Chin
    • Proceedings of the KIPE Conference
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    • 2005.07a
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    • pp.99-101
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    • 2005
  • A gate driver with Boot-strap chain is proposed to drive Multi-level PDP sustain switches. The proposed gate driver uses only one boot-strap capacitor and one diode per each MOSFETs switch without floating power supply. By adoption of this gate driver circuits, the size, weight and the cost of the drivel board can be reduced.

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Analysis of Two-step programming characteristics of the flash EEPROM's (Flash EEPROM의 two-step 프로그램 특성 분석)

  • 이재호;김병일;박근형;김남수;이형규
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.34D no.9
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    • pp.56-63
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    • 1997
  • There generally exists a large variation in the thereshold voltages of the flash EEPROM cells after they are erased by using th fowler-nordheim tunneling, thereby getting some cells to be overeased. If the overerased cells are programmed with the conventional one-step programming scheme where an 12-13V pulse with the duration of 100.mu.S is applie don the control gate for the programming, they can suffer from the significant degradation of the reliability of the gate oxide. A two-step programming schem, where an 8/12 V pulse with a duration of 50.mu.S for each voltage is applied on the control gate for the programming, has been studied to solve the problem. The experimental results hav eshown that there is little difference in the programming characteristics between those two schemes, whereas the degradation of the gate oxide due to the programming can be significantly reduced with the two-step programming scheme compared to that with the one-step programming scheme. This is possibly because the positive charge stored in the floating gate of the overerased cells is compensate dwith the electrons injected into the floating gate while the 8V pulse is applied on the control gate, which leaves the overerased cells in the normally erased state after the duration of the 8V pulse.

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Graphene for MOS Devices

  • Jo, Byeong-Jin
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2012.05a
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    • pp.67.1-67.1
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    • 2012
  • Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

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