• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 A
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• pp.233-236
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• 2001

Parallel operation scheme to several transformers is adopted because of the load increase, economic problem, or load shedding. For the transformer's parallel operation, loads proportional to each transformer's capacity must be allotted, and circulation currents must be limited as much as without causing any problem in a real operation. But, both transformers in parallel operation can be tripped when either faults at lower voltage side of a transformer or faults in a bus occurs. Therefore, parallel operation scheme to distribution transformers in Korea is not adopted in a normal state but only when loaded or load-shedded. These are due to the insufficiency of the construction in communication network and AVR scheme. Besides that, those are because bus bar protection scheme to lower voltage side of a transformer is not applied. In spite of enormous initial investment costs, advanced countries take so much account of power system reliability and stable supply that they adopt the parallel operation scheme in a normal state. One of the problems in parallel operation is the overheat of transformers due to the excessive circulation currents. This paper presents the scheme that controls voltages between both transformers using circulation currents that occurs in parallel operation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.31-38
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• 2016

A novel self-reference sense amplifier with parallel reading during writing operation is proposed. Read access time is improved compared to conventional self-reference scheme with fast operation speed by reducing operation steps to 1 for read operation cycle using parallel reading scheme, while large sense margin competitive to conventional destructive scheme is obtained by using self-reference scheme. The simulation was performed using standard $0.18{\mu}m$ CMOS process. The proposed self-reference sense amplifier improved not only the operation speed of less than 20 ns which is comparable to non-destructive sense amplifier, but also sense margin over 150 mV which is larger than conventional sensing schemes. The proposed scheme is expected to be very helpful for engineers for developing MRAM technology.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 19-21 Oct. 1992
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• pp.811-816
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• 1992

The objective of cell operation in CIM is to maximize system efficiency, not the cell itself. We introduce a cell operation scheme that pursues the direction. For specific cases, work center and AS/RS are closely investigated. Structures of their operation mechanism and methods of job scheduling are introduced along with an expert system developed for the scheme. The cell operation softwares developed are now under test at K.U.FMS, a model CIM plant.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 춘계학술대회 논문집
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• pp.684-690
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• 2008

LRT System Application Project is performed for the purpose of technical advancement and stabilization of K-AGT system from the viewpoint of practical use and commercialization. For those purpose, the performance test and evaluation procedure for signaling system have been developed, including the scheme of verifying the performance and function of signaling system under driverless multiple train operation environment. In this paper, multiple train operation scheme in K-AGT test line is presented. Test schemes for maintaining the safety distance between trains, operation scenario considering shunting and turning of train, and dia operation schemes in test line are reviewed while researching test vehicle features, route condition and running pattern. Additional equipments for testing each scheme are also reviewed.

• 전자공학회논문지B
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• 제30B권2호
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• pp.33-43
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• 1993

Lock mechanism is essential for synchronization on the multiprocessor systems. Lock mechanism needs to reduce the time for lock operation in low lock contention. Lock mechanism must consider the case of the high lock contention. The conventional lock control scheme in memory results in the increase of bus traffic and memory utilization in lock operation. This paper suggests a lock scheme which stores the lock data in cache and manages it efficiently to reduce the time spent in lock operation when the lock contention is low on a multiprocessor system built on HiPi-bus(Highly Pipelined bus). This paper also presents the design of the HIPi-CLOCK (Highly Pipelined bus Cache LOCK mechanism) which transfere the data from on cache to another when the lock contention is high. The designed simulator compares the conventional lock scheme which controls the lock in memory with the suggested HiPi-CLOCK scheme in terms of the RMW(Read-Modify-Write) operation time using simulated trace. It is shown that the suggested lock control scheme performance is over twice than that of the conventional method in low lock contention. When the lock contention is high, the performance of the suggested scheme increases as the number of the shared lock data increases.

• 한국통신학회논문지
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• 제41권12호
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• pp.1721-1735
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• 2016

Power-efficient base station (BS) operation is one of the important issues in future green cellular networks. Previously well-known BS operation schemes, the cell zooming scheme and the cell wilting and blossoming scheme, require tight cooperation between cells in cellular networks. With the previous schemes, the non-cooperative BSs of a serving cell and neighboring cells could cause coverage holes between the cells, thereby seriously degrading the quality of service as well as the power saving efficiency of the cellular networks. In this paper, we propose a novel power-efficient BS operation scheme for green downlink heterogeneous cellular networks, in which the networks virtually adjust the coverage of a serving macrocell (SM) and neighboring macrocells (NMs) without adjusting the transmission power of the BSs when the SM is lightly loaded, and the networks turn off the BS of the SM when none of active users are associated with the SM. Simulation results show that our proposed scheme significantly improves the power saving efficiency without degrading the quality of service (e.g., system throughput) of a downlink heterogeneous LTE network and outperforms the previous schemes in terms of system throughput and power saving efficiency. In particular, with the proposed scheme, macrocells are able to operate independently without the cooperation of a SM and NMs for green heterogeneous cellular networks.

• 한국통신학회논문지
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• 제36권6C호
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• pp.403-411
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• 2011

본 논문에서는 주파수 선택적 페이딩 채널에서 (frequency selective fading channels) 인지 무선 통신을 위한 Alamouti 코딩 기반 협력 전송 기법을 제안한다. 제안한 기법은 시간 반전 연산과 (time-reversal operation) 공액 복소 연산을 (conjugate operation) 사용하는 기존 기법과 다르게 소스 노드에서의 간단한 심볼 조합을 통해 목적지 노드에서 Alamouti 부호 구조를 획득한다. 모의실험 결과를 통하여 제안한 기법의 다이버시티 이득 차수가 기존 기법의 다이버시티 이득 차수보다 높은 것을 확인한다.

• 한국태양에너지학회 논문집
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• 제37권3호
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• pp.13-22
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• 2017

Anti-islanding scheme of grid-connected inverter is a key function of standards compliance, since unintentional islanding results in safety hazards, reliability, and many other issues. Therefore, many anti-islanding schemes have been researched, however, most of them have problems, which deteriorate performance of islanding detection under parallel-operation. Therefore, this paper proves the reason of problems and proposes a new anti-islanding scheme that has precise islanding detection under parallel-operation in single-phase and three-phase system. Finally, both simulation and experimental result validate the proposed scheme.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제15권4호
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• pp.1521-1537
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• 2021

Through information hiding technique, secret message can be hidden in pictures. Stego-image quality and hiding capacity are two important metrics for information hiding. To enhance these metrics, many schemes were proposed by scholars in recent years. Some of them are effective and successful, but there is still a room for further improvement. A high capacity information hiding scheme (PAMO, Pixel-value Adjustment with Modulus Operation Algorithm) is introduced in this paper. PAMO scheme uses pixel value adjustment with modulus operation to hide confidential data in cover-image. PAMO scheme and some referenced schemes are implemented in Python and experiments are carried out to evaluate their performance. In the experiments, PAMO scheme shows better performance than other methods do. When secret message length is less than 72000 bits, the highest hiding capacity of PAMO can reach 7 bits per pixel, at the same time the PSNR of stego-images is greater than 30 dB.

• Journal of Information Technology Applications and Management
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• 제13권4호
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• pp.257-271
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• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However, we need to improve traditional Indexing scheme such as B-Tree due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal, we devise a new indexing scheme called F-Tree. F-Tree improves tree operation performance by compressing pointers and keys in tree nodes and rewriting the nodes without a slow erase operation in node insert/delete processes. Based on the results of the performance evaluation, we conclude that F-Tree indexing scheme outperforms the traditional indexing scheme.