• Transactions on Electrical and Electronic Materials
• /
• v.16 no.5
• /
• pp.254-259
• /
• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

• Journal of IKEEE
• /
• v.27 no.4
• /
• pp.399-404
• /
• 2023

In this paper, we analyzed the current path in the O/N/O (Oxide/Nitride/Oxide) structure of 3D NAND Flash memory and in the O/N/F (Oxide/Nitride/Ferroelectric) structure where the blocking oxide is replaced by a ferroelectric. In the O/N/O structure, when V_read is applied, a current path is formed on the backside of the channel due to the E-fields of neighboring cells. In contrast, the O/N/F structure exhibits a current path formed on the front side due to the polarization of the ferroelectric material, causing electrons to move toward the channel front. Additionally, we performed an examination of device characteristics considering channel thickness and channel length. The analysis results showed that the front electron current density in the O/N/F structure increased by 2.8 times compared to the O/N/O structure, and the front electron current density ratio of the O/N/F structure was 17.7% higher. Therefore, the front current path is formed more effectively in the O/N/F structure than in the O/N/O structure.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.256-256
• /
• 2012

Oxide semiconductors such as zinc tin oxide (ZTO) or indium gallium zinc oxide (IGZO) have attracted a lot of research interest owing to their high potential for application as thin film transistors (TFTs) [1,2]. However, the instability of oxide TFTs remains as an obstacle to overcome for practical applications to electronic devices. Several studies have reported that the electrical characteristics of ZnO-based transistors are very sensitive to oxygen, hydrogen, and water [3,4,5]. To improve the reliability issue for the amorphous InGaZnO (a-IGZO) thin-film transistor, back channel passivation layer is essential for the long term bias stability. In this study, we investigated the instability of amorphous indium-gallium-zinc-oxide (IGZO) thin film transistors (TFTs) by the back channel contaminations. The effect of back channel contaminations (humidity or oxygen) on oxide transistor is of importance because it might affect the transistor performance. To remove this environmental condition, we performed vacuum seasoning before the deposition of hybrid passivation layer and acquired improved stability. It was found that vacuum seasoning can remove the back channel contamination if a-IGZO film. Therefore, to achieve highly stable oxide TFTs we suggest that adsorbed chemical gas molecules have to be eliminated from the back-channel prior to forming the passivation layers.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.34 no.2
• /
• pp.142-147
• /
• 2021

We present a subthreshold swing model for a symmetric junctionless double gate MOSFET. The scale length λ1 required to obtain the potential distribution using the Poisson's equation is a criterion for analyzing the short channel effect by an analytical model. In general, if the channel length Lg satisfies Lg > 1.5λ1, it is known that the analytical model can be sufficiently used to analyze short channel effects. The scale length varies depending on the channel and oxide thickness as well as the dielectric constant of the channel and the oxide film. In this paper, we obtain the scale length for a constant permittivity (silicon and silicon dioxide), and derive the relationship between the scale length and the channel length satisfying the error range within 5%, compared with a numerical method. As a result, when the thickness of the oxide film is reduced to 1 nm, even in the case of Lg < λ1, the analytical subthreshold swing model proposed in this paper is observed to satisfy the error range of 5%. However, if the oxide thickness is increased to 3 nm and the channel thickness decreased to 6 nm, the analytical model can be used only for the channel length of Lg > 1.8λ1.

• Journal of IKEEE
• /
• v.27 no.3
• /
• pp.303-307
• /
• 2023

In this paper, the creation of an Electron-Hole Pair due to Total Ionizing Dose (TID) effects inside the oxide of a Buried Channel Array Transistor (BCAT) device is induced, resulting in an increase in leakage current and threshold due to an increase in hole trap charge at the oxide interface. By comparing and simulating changes in voltage with the previously proposed Partial Isolation Buried Channel Array Transistor (Pi-BCAT) structure, the characteristics in leakage current and threshold voltage changed regardless of the increased oxide area of the Pi-BCAT device, compared to the asymmetrically doped BCAT structure. It shows superiority.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.9
• /
• pp.729-734
• /
• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• ETRI Journal
• /
• v.31 no.6
• /
• pp.653-659
• /
• 2009

We have investigated the channel protection layer (PL) effect on the performance of an oxide thin film transistor (TFT) with a staggered top gate ZnO TFT and Al-doped zinc tin oxide (AZTO) TFT. Deposition of an ultra-thin PL on oxide semiconductor films enables TFTs to behave well by protecting the channel from a photo-resist (PR) stripper which removes the depleted surface of the active layer and increases the carrier amount in the channel. In addition, adopting a PL prevents channel contamination from the organic PR and results in high mobility and small subthreshold swings. The PL process plays a critical role in the performance of oxide TFTs. When a plasma process is introduced on the surface of an active layer during the PL process, and as the plasma power is increased, the TFT characteristics degrade, resulting in lower mobility and higher threshold voltage. Therefore, it is very important to form an interface using a minimized plasma process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.31 no.5
• /
• pp.278-282
• /
• 2018

We propose a SPICE model of drain-induced barrier lowering (DIBL) for a junctionless cylindrical surrounding gate (JLCSG) MOSFETs. To this end, the potential distribution in the channel is obtained via the Poisson equation, and the threshold voltage model is presented for the JLCSG MOSFET. In a JLCSG nano-structured MOSFET, a channel radius affects the carrier transfer as well as the channel length and oxide thickness; therefore, DIBL should be expressed as a function of channel length, channel radius, and oxide thickness. Consequently, it can be seen that DIBLs are proportional to the power of -3 for the channel length, 2 for the channel radius, 1 for the thickness of the oxide film, and the constant of proportionality is 18.5 when the SPICE parameter, the static feedback coefficient ${\eta}$, is between 0.2 and 1.0. In particular, as the channel radius and the oxide film thickness increase, the value of ${\eta}$ remains nearly constant.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.252-253
• /
• 2011

ZnO-based thin film transistors (TFTs) are of great interest for application in next generation flat panel displays. Most research has been based on amorphous indium-gallium-zinc-oxide (IGZO) TFTs, rather than single binary oxides, such as ZnO, due to the reproducibility, uniformity, and surface smoothness of the IGZO active channel layer. However, recently, intrinsic ZnO-TFTs have been investigated, and TFT- arrayss have been demonstrated as prototypes of flat-panel displays and electronic circuits. However, ZnO thin films have some significant problems for application as an active channel layer of TFTs; it was easy to change the electrical properties of the i-ZnO thin films under external conditions. The variable electrical properties lead to unstable TFTs device characteristics under bias stress and/or temperature. In order to obtain higher performance and more stable ZnO-based TFTs, HZO thin film was used as an active channel layer. It was expected that HZO-TFTs would have more stable electrical characteristics under gate bias stress conditions because the binding energy of Hf-O is greater than that of Zn-O. For deposition of HZO thin films, Hf would be substituted with Zn, and then Hf could be suppressed to generate oxygen vacancies. In this study, the fabrication of the oxide-based TFTs with HZO active channel layer was reported with excellent stability. Application of HZO thin films as an active channel layer improved the TFT device performance and bias stability, as compared to i-ZnO TFTs. The excellent negative bias temperature stress (NBTS) stability of the device was analyzed using the HZO and i-ZnO TFTs transfer curves acquired at a high temperature (473 K).

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.5
• /
• pp.992-997
• /
• 2016

This paper analyzes the deviation of tunneling current for the ratio of top and bottom gate oxide thickness of short channel asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current significantly increases if channel length reduces to 5 nm. This short channel effect occurs for asymmetric DGMOSFET having different top and bottom gate oxide structure. The ratio of tunneling current in off current with parameters of channel length and thickness, doping concentration, and top/bottom gate voltages is calculated in this study, and the influence of tunneling current to occur in short channel is investigated. The analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for the ratio of top and bottom gate oxide thickness in short channel asymmetric DGMOSFET, specially according to channel length, channel thickness, doping concentration, and top/bottom gate voltages.