• Title, Summary, Keyword: PLL synchronization

Search Result 82, Processing Time 0.03 seconds

Adaptive Neural PLL for Grid-connected DFIG Synchronization

  • Bechouche, Ali;Abdeslam, Djaffar Ould;Otmane-Cherif, Tahar;Seddiki, Hamid
    • Journal of Power Electronics
    • /
    • v.14 no.3
    • /
    • pp.608-620
    • /
    • 2014
  • In this paper, an adaptive neural phase-locked loop (AN-PLL) based on adaptive linear neuron is proposed for grid-connected doubly fed induction generator (DFIG) synchronization. The proposed AN-PLL architecture comprises three stages, namely, the frequency of polluted and distorted grid voltages is tracked online; the grid voltages are filtered, and the voltage vector amplitude is detected; the phase angle is estimated. First, the AN-PLL architecture is implemented and applied to a real three-phase power supply. Thereafter, the performances and robustness of the new AN-PLL under voltage sag and two-phase faults are compared with those of conventional PLL. Finally, an application of the suggested AN-PLL in the grid-connected DFIG-decoupled control strategy is conducted. Experimental results prove the good performances of the new AN-PLL in grid-connected DFIG synchronization.

Phase Locked Loop based Time Synchronization Algorithm for Telemetry System (텔레메트리 시스템을 위한 PLL 기반의 시각동기 알고리즘)

  • Kim, Geon-Hee;Jin, Mi-Hyun;Kim, Bok-Ki
    • Journal of Advanced Navigation Technology
    • /
    • v.24 no.4
    • /
    • pp.285-290
    • /
    • 2020
  • This paper presents a time synchronization algorithm based on PLL for application to telemetry systems and implement FPGA logic. The large aircraft of the telemetry system acquires status information through each distributed acquisition devices and analyzes the flight status in real time. For this reason, time synchronization between systems is important to improve precision. This paper presents a PLL based time synchronization algorithm that is less complex than other time synchronization methods and takes less time to process data because there is minimized message transmission for synchronization. The validity of proposed algorithm is proved by simulation of Python. And the VHDL logic was implemented in FPGA to check the time synchronization performance.

Analysis for bit synchronization using charge-pump phase-locked loop (비트 동기 Charge-pump 위상 동기 회로의 해석)

  • 정희영;이범철
    • Journal of the Korean Institute of Telematics and Electronics S
    • /
    • v.35S no.1
    • /
    • pp.14-22
    • /
    • 1998
  • The Mathematic model of bit synchronization charge-pump Phase Locked Loop (PLL) is presented which takes into account the aperiodic reference pulses and the leakage current of the loop filter. We derive theoreitcal static phase error, overload and stability of bit synchronization charge-pump PLL using presented model and compare it with one of the conventional charge-pump PLL model. We can analysis bit synchronization charge-pump PLL exactly because our model takes into account the leakage current of the loop filter and aperiodic input data which are the charateristics of bit synchronization charge-pump PLL. We also verify it using HSPICE simulation with a bity synchronizer circuit.

  • PDF

Synchronization for IR-UWB System Using a Switching Phase Detector-Based Impulse Phase-Locked Loop

  • Zheng, Lin;Liu, Zhenghong;Wang, Mei
    • ETRI Journal
    • /
    • v.34 no.2
    • /
    • pp.175-183
    • /
    • 2012
  • Conventional synchronization algorithms for impulse radio require high-speed sampling and a precise local clock. Here, a phase-locked loop (PLL) scheme is introduced to acquire and track periodical impulses. The proposed impulse PLL (iPLL) is analyzed under an ideal Gaussian noise channel and multipath environment. The timing synchronization can be recovered directly from the locked frequency and phase. To make full use of the high harmonics of the received impulses efficiently in synchronization, the switching phase detector is applied in iPLL. It is capable of obtaining higher loop gain without a rise in timing errors. In different environments, simulations verify our analysis and show about one-tenth of the root mean square errors of conventional impulse synchronizations. The developed iPLL prototype applied in a high-speed ultra-wideband transceiver shows its feasibility, low complexity, and high precision.

Analysis of a Synchronizing PLL System for Single-phase Grid-tie Inverters (단상 그리드연결형 인버터의 동기화를 위한 PLL 시스템 해석)

  • Tran, Quang-Vinh;Chun, Tae-Won;Lee, Hong-Hee;Kim, Heung-Geun;Nho, Eui-Cheol
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.13 no.6
    • /
    • pp.447-452
    • /
    • 2008
  • In the paper, the product-type PLL system, which is so suitable for synchronizing a single phase grid voltage is designed. The PLL system is modelled with the small signal analysis. Both the cut-off frequency of low pass filter and the optimal gain are derived by considering the transient response for synchronization as well as a distortion of synchronization signal. Through the simulation studies and experimental results, the transient response and ripple component of synchronization signal are investigated with a variation of both the cut-off frequency and gain in order to verify the performance of design.

Synchronization Techniques for Single-Phase and Three-Phase Grid Connected Inverters using PLL Algorithm (PLL 알고리즘을 사용한 단상 및 3상 계통연계형 인버터의 동기화 기법)

  • Chun, Tae-Won;Lee, Hong-Hee;Kim, Heung-Geun;Nho, Eui-Cheol
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.16 no.4
    • /
    • pp.309-316
    • /
    • 2011
  • A PLL system has widely used for synchronizing the grid voltage at the grid-connected inverter for supplying power from the PV generation systems. In this paper, a PLL algorithm without both the loop filter and PI controller is suggested for improving the performance of synchronization at the single-phase and three-phase grid connected inverters. In order that the output voltage of a phase detector in the PLL has only a dc voltage, and it approaches to 0 when the synchronization signal is locked to the grid voltage, the feedback signals are determined by using two-phase voltages. After the PLL system with a proportional controller is modelled with the small signal analysis, the stability and steady-state error are investigated. Through the simulation studies and experimental results, the performances of the proposed PLL algorithm are verified.

A Method to Improve the Performance of Phase-Locked Loop (PLL) for a Single-Phase Inverter Under the Non-Sinusoidal Grid Voltage Conditions (비정현 계통 전압하에서 단상 인버터의 PLL 성능 개선 방법)

  • Khan, Reyyan Ahmad;Ashraf, Muhammad Noman;Choi, Woojin
    • Proceedings of the KIPE Conference
    • /
    • /
    • pp.7-8
    • /
    • 2017
  • The Phase-Locked Loop (PLL) is widely used in grid-tie inverter applications to achieve the synchronization between the inverter and the grid. However, its performance is deteriorated when the grid voltage is not pure sinusoidal due to the harmonics and the frequency deviation. Therefore it is important to design a high performance phase-locked loop (PLL) for the single phase inverter applications to guarantee the quality of the inverter output. In this paper a simple method to improve the performance of the PLL for the single phase inverter is proposed. The proposed PLL is able to accurately estimate the fundamental frequency component of the grid voltage even in the presence of harmonic components. In additional its transient response is fast enough to track a change in grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

  • PDF

A Method to Improve the Performance of Phase-Locked Loop (PLL) for a Single-Phase Inverter Under the Non-Sinusoidal Grid Voltage Conditions (비정현 계통 전압하에서 단상 인버터의 PLL 성능 개선 방법)

  • Khan, Reyyan Ahmad;Choi, Woojin
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.23 no.4
    • /
    • pp.231-239
    • /
    • 2018
  • The phase-locked loop (PLL) is widely used in grid-tie inverter applications to achieve a synchronization between the inverter and the grid. However, its performance deteriorates when the grid voltage is not purely sinusoidal due to the harmonics and the frequency deviation. Therefore, a high-performance PLL must be designed for single-phase inverter applications to guarantee the quality of the inverter output. This paper proposes a simple method that can improve the performance of the PLL for the single-phase inverter under a non-sinusoidal grid voltage condition. The proposed PLL can accurately estimate the fundamental frequency and theta component of the grid voltage even in the presence of harmonic components. In addition, its transient response is fast enough to track a grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

Output Phase Synchronization Method of Inverter for Parallel Operation of Uninterruptible Power System (무정전전원장치 병렬운전을 위한 인버터의 출력 위상 동기화 방법)

  • Kim, Heui-Joo;Park, Jong-Myeon;Oh, Se-Hyung
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.25 no.3
    • /
    • pp.235-241
    • /
    • 2020
  • In this paper, we propose the bus/bypass synchronization phase lock loop (B-Sync PLL) method using each phase voltage controller of a parallel UPS inverter. The B-Sync PLL included in each phase voltage control system of parallel UPS inverters has the transient response and the phase synchronization error at grid normal or blackout. The validity of this method is verified by simulation and experiment. As a result, the parallel UPS inverters using the proposed method confirmed that the output phase was continuously synchronized when a grid blackout, improving the transient response characteristics for stable load power supply and equal load sharing.

A Robust PLL Technique Based on the Digital Lock-in Amplifier under the Non-Sinusoidal Grid Conditions (디지털 록인앰프를 이용한 비정현 계통하에서 강인한 PLL 방법)

  • Ashraf, Muhammad Noman;Khan, Reyyan Ahmad;Choi, Woojin
    • Proceedings of the KIPE Conference
    • /
    • /
    • pp.104-106
    • /
    • 2018
  • The harmonics and the DC offset in the grid can cause serious synchronization problems for grid connected inverters (GCIs) which leads not able to satisfy the IEEE 519 and p1547 standards in terms of phase and frequency variations. In order to guarantee the smooth and reliable synchronization of GCIs with the grid, Phase Locked Loop (PLL) is the crucial element. Typically, the performance of the PLL is assessed to limit the grid disturbances e.g. grid harmonics, DC Offset and voltage sag etc. To ensure the quality of GCI, the PLL should be precise in estimating the grid amplitude, frequency and phase. Therefore, in this paper a novel Robust PLL technique called Digital Lock-in Amplifier (DLA) PLL is proposed. The proposed PLL estimate the frequency variations and phase errors accurately even in the highly distorted grid voltage conditions like grid voltage harmonics, DC offsets and grid voltage sag. To verify the performance of proposed method, it is compared with other six conventional used PLLs (CCF PLL, SOGI PLL, SOGI LPF PLL, APF PLL, dqDSC PLL, MAF PLL). The comparison is done by simulations on MATLAB Simulink. Finally, the experimental results are verified with Single Phase GCI Prototype.

  • PDF