• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.27-33
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• 2000

Gardner’s algorithm is one of the useful algorithm for NDD(Non-Decision Directed) symbol synchronization in PAM communications. But the algorithm has a weak point such as pattern noises increasing in multi-level PAM. To insert a pre-filter in the algorithm is able to reduce timing jitter and pattern noise. In this paper, we analyze statistical properties of NDD algorithm to find an optimal parameter of the pre-filter for improving timing jitter and PLL locking. As a simulation result, optimum value of pre-filter parameter, $\beta$, is 0.3 and 0.5 at the roll off factor of the channel, $\alpha$, is 0.5 and 1.0, respectively. Optimum parameters of the pre-filter for clock synchronization of all-digital 256-QAM demodulator is shown in the results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12A
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• pp.1120-1135
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• 2005

In this paper, We have design and implement the network synchronization module for NG-SDH system having 120 Gbps capacity. and also evaluate the performance of it. We also propose analyzing algorithm clock characterisrics on NG-SDH node clock based on the evaluation results.

• Journal of Advanced Marine Engineering and Technology
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• v.28 no.2
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• pp.347-353
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• 2004

Neural oscillator can be applied to oscillator systems such as analysis of image information, voice recognition and etc, Conventional learning algorithms(Neural Network or EBPA(Error Back Propagation Algorithm)) are not proper for oscillatory systems with the complicate input patterns because of its too much complex structure. However, these problems can be easily solved by using a synchrony characteristic of neural oscillator with PLL(phase locked loop) function and a simple Hebbian learning rule, Therefore, in this paper, it will introduce an technique for Recognition of the Korean Character using Phase Synchronization Neural Oscillator and will show the result of simulation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.10
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• pp.73-82
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• 2015

This paper proposes an ripple reduction algorithm and analyzes the effects of offset and scale errors generated by voltage sensor while measuring grid voltage in grid-tied single-phase inverters. Generally, the grid-connected inverter needs to detect the phase angle information by measuring grid voltage for synchronization, so that the single-phase inverter can be accurately driven based on estimated phase angle information. However, offset and scale errors are inevitably generated owing to the non-linear characteristics of voltage sensor and these errors affect that the phase angle includes 1st harmonic component under using SRF-PLL(Synchronous Reference Frame - Phase Locked Loop) system for detecting grid phase angle. Also, the performance of the overall system is degraded from the distorted phase angle including the specific harmonic component. As a result, in this paper, offset and scale error due to the voltage sensor in single-phase grid connected inverter under SRF-PLL is analyzed in detail and proportional resonant controller is used to reduce the ripples caused by the offset error. Especially, the integrator output of PI(Proportional Integral) controller in SRF-PLL is selected as an input signal of the proportional resonant controller. Simulation and experiment are performed to verify the effectiveness of the proposed algorithm.

• The KIPS Transactions:PartC
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• v.11C no.6 s.95
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• pp.835-842
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• 2004

In this paper, we have analyzed the MC-DS/CDMA system with input signal synchronized completely through adjustment of the gain in the PLL loop, by using the hybrid SC/MRC-(2/3) technique, which is said to one of the optimal diversity techniques under the multi-path fading environment, assuming that phase error is defined to the phase difference between the received signal from the multi-path and the reference signal in the PLL of the receiver. Also, assuming that the regarded radio channel model for the mobile communication is subject to the Nakagami-m fading channel, we have developed the expressions and performed the simulation under the consideration of various factor, in the MC/DS-CDMA system with the hybrid SC.MRC-(2/3) diversity method, such as the Nakagami fading index(m), $the\;number\;of\;paths\;(L_p),$ the number of hybrid SC.MRC-(2/3) $diversity\;branches\;(L,\;L_c),$ the number of users (K), the number of subcarriers (U), and the gain in the PLL loop. As a result of the simulation, it has been confirmed that the performance improvement of the system can be achieved by adjusting properly the PLL loop in order for the MC/DS-CDMA system with the hybrid SC/MRC-(2/3) diversity method to receive a fully synchronized signal. And the value of the gain in the PLL loop should exceed 7dB in order for the system to receive the signal with prefect synchronization, even though there might be a slight difference according to the values of the fading index and the spread processing gain of the subcarrier.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2003.05a
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• pp.319-323
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• 2003

In this paper, we propose a hybrid transceiver for underwater acoustic communication, which allows the system to reduce complexity and increase robustness in time variant underwater channel environments. It is designed in the digital domain except for amplifiers and implemented by using a multiple digital signal processors (DSPs) system. The digital modulation technique is quadrature phase shift keying (QPSK) and frame synchronization is an energy (non-coherent) detection scheme based on the quadrature receiver structure. DSP implementation is based on block data parallel architecture (BDPA). We shaw experimental results in th? underwater anechoic basin at KRISO. The results indicate that the frame synchronization is performed without PLL. Also, we shaw that the adaptive equalizer can compensate frame synchronization error and the correction capability is dependent on the length of equalizer.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1101-1107
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• 2017

In this paper, a robust and fast grid synchronization method of a three-phase power converter is proposed. The amplitude and phase information of grid voltages are essential for power converters to be properly connected into the utility. The phase-lock-loop in synchronous reference frame has been widely adopted for the three-phase converter system since it shows a satisfactory performance under balanced grid voltages. However, power converters often operate under abnormal grid conditions, i.e. unbalanced by grid faults and frequency variations, and thus a proper active and reactive power control cannot be guaranteed. The proposed method adopts a second order generalized integrator in synchronous reference frame to detect positive sequence components under unbalanced grid voltages. The proposed method has a fast and robust performance due to its higher gain and frequency adaptive capability. Simulation and experimental results show the verification of the proposed synchronization algorithm and the effectiveness to detect positive sequence voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.807-813
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• 2009

A Satellite transponder is the Communication system to process signal with up-link signal recovery, and transmit to ground station through down-link. The orbit flight in the deep space causes high doppler shift in the received signals from the ground station so that the Carrier recovery and fast synchronization system are essential for the transponder system. The conventional analog transponder is employing the system's carrier recovery along with the PLL (Phase Locked Loop) designed for satellite's operation. This paper presents a digital carrier recovery scheme which can provide more reliable and software reconfigurable implementation technique for satellite transponder system without verifying scheme along with transponder designed for short distance or deep space satellite.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.7B
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• pp.989-995
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• 2001

흔히 전송매체와 연결되는 물리계층에서는 수신된 데이터열에서 동기를 획득하는 과정이 필요하다. 기가비트 이더넷에서는 PMA에서 PCS로 데이터열을 전송할 때 62.5MHz 두 개의 클럭에 맞추어 교대로 보내는 절차를 표준안으로 채택하고 있기 때문에 수신된 데이터열을 처리하기 위한 125MHz 클럭을 생성해내는 PLL이 필요하다. 그러나 PLL은 구현하기가 어렵다. 다른 대안들로는 FIFO를 활용하는 방법과 62.5MHz 클럭을 이용한 이중 데이터열 처리 방법 등이 있다. FIFO를 이용한 방법에서는 오버플로우가 발생할 수 있으며, 이중 데이터열 처리 방법에서는 표준안과 다른 별도의 수신부 설계가 필요하다. 본 논문에서는 언급한 방법들을 사용하지 않으면서도 표준안을 따르며 비용 효과적인 하나의 방안으로 송신부 클럭에 수신된 데이터열을 재정렬 시킬 수 있는 DSM(Divide-Select-Merge) 방법을 제안한다.