• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.62-68
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• 1996

A CMOS transmitter ASIC for the ATM switching system etc., was designed to transmit 155.52 Mbps serial data transformed from 19.44 Mbps parallel data. 155.52 MHz clock for synchronization of data is genrated using reference 19.44 MHz clock by an analog PLL while parallel to serial data conversion is done by a digital circuit. Circuit simulations confirm that PLL locking and data conversion are accomplished successfully. The area of the designed ASIC chip is 1.3${\times}1.0mm^2$. The locking time and the power consumption of the chip are about 600 nsec and less than 150 mW, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.9 no.1
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• pp.25-30
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• 1972

Data Communication by sending pulse train and verifying the lock-in of a phase locked loop in receiving end is studied. The noise rejection property inherent to PLL is analysed. By using about six pulses in a train, data transimission rate of 20k bit/sec. in a telephone cable is achieved, thus permitting high speed data communication and an exellent immunity against noise.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.72-73
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• 2013

본 논문은 계통 연계형 인버터에서 LPN 필터를 이용한 계통 위상 추종 방법을 제안한다. 기존의 FFT를 이용한 계통 위상 추종 알고리즘의 한주기 평균 계산부를 LPN 필터로 대체하여 위상 추종 성능을 개선하였다. 기존의 FFT-PLL의 경우 SRF-PLL과 달리 별도의 PI 게인 튜닝이 필요 없으며, 고조파와 같은 노이즈에 강인한 특징을 가진다. 하지만 위상 이동시에 새로운 위상을 추종하기 위해서 한주기 소요된다. 따라서 본 논문에서는 LPN 필터를 사용하여 반주기 이내에 추종할 수 있도록 성능을 개선하였다. 제안된 위상 추종 전략의 타당성을 실험을 통하여 검증하였다.

• ETRI Journal
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• v.30 no.4
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• pp.546-554
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• 2008

Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.260-268
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• 1990

This paper investigates the design of a frequency hopping FSK tranceiver system, where the system enhancements are made in the following three aspects: dual frequency synthesiszation for the increased hopping rate, linearization of VCO gain in PLL to improve BFSK modulation characteristics, and fast code synchronization by the matched filter method.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.506-509
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• 2001

A high power U.P.S system utilizing the parallel connection of low power U.P.S is developed. For the purpose of elimination the circular current between U.P.S.s, a digital circuit is employed. Furthermore a double phase synchronization and an interphase reactor are used to eliminate the circular current and the voltage ripples caused by the system parameter unbalances of parall connected U.P.S.s. The digital controller is implemented with ADSP21061 as aspect of a functional convenience.

• Journal of the Korea Society of Computer and Information
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• v.5 no.3
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• pp.106-111
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• 2000

In this paper, we designed the DCO controller of frequency synthesizer by combing the m DS, DDS, and PLL methods to improve the performances(transition time, stability, re Designed DCO controller used parallel processing and pattern matching techniques. The designed DCO controller in this thesis profits the rapid and exact synchronization wh handed off in the mobile communication.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.1
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• pp.93-99
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• 2004

Neural oscillator can be applied to oscillatory systems such as analyses of image information, voice recognition and etc. Conventional EBPA (Error back Propagation Algorithm) is not proper for oscillatory systems with the complicate input`s patterns because of its tedious training procedures and sluggish convergence problems. However, these problems can be easily solved by using a synchrony characteristic of neural oscillator with PLL(Phase Locked Loop) function and by using a simple Hebbian learning rule. Therefore, in this paper, a technique for Recognition of the Korean Alphabet using Phase Synchronized Neural Oscillator was introduced.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.3 no.2
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• pp.11-17
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• 2004

In this paper we propose a new conceptual system for a network clock in which all node clocks are simultaneously synchronized to the national standard by intermediation parameter of satellite time. Experiments have shown the possibility of its adoption by real networks. The new proposed method has various structural benefits, in particular all node clocks can be kept at the same hierarchical quality in contrast to the existing method. The measurement results show that the accuracy of the experimental slave clock system can be kept within a few parts In 1012 and the MTIE (Maximum Time Interval Error) sufficiently meets ITU-T G.811 for the primary reference clock. A prototype system with fully automatic operational functions has been realized at present and is expected to be directly used for communication network synchronization in the near future.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1765-1773
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• 1997

The communication systems which include PLL may have cycle clip problem because of channel noise. The cycle slip problem occurs the synchronization loss of communication system and it may be fatal to the synchronous stream cipher system. While continuous resynchronization is used to lessen the risk of synchronization it has some problems. In this paper, we propose the method which solve the problems by using continuous resynchronization with the clock recovery technique. If the counted value of real clock pulse in reference duration is not same as that of normal state, we decide the cycle slip has occurred. The damaged clock by cycle slip is compensated by adding or subtracting the clock pulse according to the type of cycle slip. It reduced the time for resynchronization by twenty times. It means that 17.8% of data for transmit is compressed.