• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.4
• /
• pp.807-812
• /
• 2015

In RFID system, when multiple tags respond simultaneously, a collision can occur. A method that solves this collision is referred as anti-collision algorithm. In 13.56MHz RFID system of Auto-ID center, STAC protocol is defined as an anti-collision algorithm for multiple tag reading. The PS algorithm divides the tags within the identification range of reader into smaller groups by increasing the transmission power incrementally and identifies them. In this paper, we propose a STAC/PS algorithm that the PS algorithm is applied in the STAC protocol. Through simulations, it is demonstrated that the collision rate for the proposed algorithm is about 50% lower than STAC protocol. Therefore, the STAC/PS algorithm can achieve faster tag identification speed compared with STAC protocol due to the low collision rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.05a
• /
• pp.547-549
• /
• 2014

In RFID systems, the performance for the tag identification is closely related with the tag collision, which is caused by the simultaneous transmission. The PS algorithm divides the tags within the identification range of reader into smaller groups by increasing the transmission power incrementally and identifies them. This algorithm uses the fixed frame size at every scan. Therefore, it is anticipated that the performance of PS algorithm can be variously shown according to the number of tags, frame size, and power level increase. In this paper, we analize the performance of PS algorithm according to the frame length and power level increase.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.10a
• /
• pp.712-714
• /
• 2016

The PS algorithm divides the tags within the identification range of reader into smaller groups by increasing the transmission power incrementally and identifies them. In 13.56MHz RFID system of Auto-ID center, STAC protocol is defined as an anti-collision algorithm for multiple tag reading. In this paper, we propose a STAC/PS algorithm that the PS algorithm is applied in the STAC protocol. The simulation results show that the STAC/PS algorithm can achieve faster tag identification speed compared with STAC protocol due to the low collision rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.615-617
• /
• 2014

The PS algorithm divides the tags within the identification range of reader into smaller groups by increasing the transmission power incrementally and identifies them. This algorithm uses the fixed frame size at every scan. Therefore, it has problems that the performance of PS algorithm can be variously shown according to the number of tags, frame size, and power level increase. In this paper, we propose an EPS algorithm that allocates the optimal frame size by estimating the number of tags at each scan.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.5
• /
• pp.931-936
• /
• 2016

The PS algorithm divides the number of tags within the identification range of reader into smaller groups by increasing the transmission power incrementally and identifies them. It limits the number of responding tags by grouping the tags within the identification range of the reader, and thus can reduce the probability of tag collision. Also, in the PS algorithm, the reader takes advantages of the difference of identification ranges. This algorithm uses the fixed frame size at every scan. Therefore, it has problems that the performance can be shown variously according to the number of tags and frame size. In this paper, we propose an EPS algorithm that allocates the optimal frame size by estimating the number of tags at each scan, and apply it into the STAC protocol. The simulation results showed that STAC/EPS algorithm can improve the identification delay about 45% compared with STAC protocol. Also, it provides a stable identification delay regardless of power level increase.

• Journal of Internet Computing and Services
• /
• v.10 no.1
• /
• pp.1-9
• /
• 2009

In this paper, A pipeline structured-degree computationless modified Euclidean (PS-DCME) algorithm is proposed, which can be used for a RS(23,17) decoder for MB-OFDM system. PS-DCME algorithm requires a state machine instead of the degree computation and comparison circuits, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. We have implemented a RS(23,17) decoder with PS-DCME using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 19,827.

• The KIPS Transactions:PartC
• /
• v.16C no.5
• /
• pp.661-668
• /
• 2009

The Extended real-time Polling Service (ErtPS) is proposed tosupport QoS of VoIP service with silence suppression which generates variable size data packets in IEEE 802.16e systems. If the silence is suppressed, VoIP should support Comfort Noise Generation (CNG) which generates comfort noise for receiver's auditory sense to notify the status of connection to the user. CNG mode in silent-period generates a data with lower bit rate at long packet transmission intervals in comparison with talk-spurt. Therefore, if the ErtPS, which is designed to support service flows that generate data packets on a periodic basis, is applied to silent-period, resources of the uplink are used inefficiently. In this paper, we proposed the Improved ErtPS algorithm for efficient resource utilization of the silent-period in VoIP traffic supporting CNG. In the proposed algorithm, the base station allocates bandwidth depending on the status of voice at the appropriate interval by havingthe user inform the changes of voice status. The Improved ErtPS utilizes the Cannel Quality Information Channel (CQICH) which is an uplink subchannel for delivering quality information of channel to the base station on a periodic basis in 802.16e systems. We evaluated the performance of proposed algorithm using OPNET simulator. We validated that proposed algorithm improves the bandwidth utilization of the uplink and packet transmission latency

• Journal of Institute of Control, Robotics and Systems
• /
• v.16 no.1
• /
• pp.96-100
• /
• 2010

This paper proposes novel genetic design of optimal classifier ensemble for vehicle detection using Genetic Algorithm with Varying Population Size (GAVaPS). Recently, many classifiers are used in classifier ensemble to deal with tremendous amounts of data. However the problem has a exponential large search space due to the increasing the number of classifier pool. To solve this problem, we employ the GAVaPS which outperforms comparison with simple genetic algorithm (SGA). Experiments are performed to demonstrate the efficiency of the proposed method.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.18 no.6
• /
• pp.871-875
• /
• 2008

This paper deals with the feature selection for multiple k-nearest neighbor (k-NN) classifiers using Genetic Algorithm with Varying reputation Size (GAVaPS). Because we use multiple k-NN classifiers, the feature selection problem for them is vary hard and has large search region. To solve this problem, we employ the GAVaPS which outperforms comparison with simple genetic algorithm (SGA). Further, we propose the efficient combining method for multiple k-NN classifiers using GAVaPS. Experiments are performed to demonstrate the efficiency of the proposed method.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.4
• /
• pp.520-527
• /
• 2016

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.