• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.36-38
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• 2018

As the battery capacity requirement increases, battery cells are connected in a parallel configuration. However, the sharing current of each battery cell becomes unequal due to the imbalance between cell's impedance which results the mismatched states of charge (SOC). The conventional fixed-resistance balancing methods have a limitation in battery equalization performance and system efficiency. This paper proposes a battery equalization method based on dynamic resistance technique, which can improve equalization performance and reduce the loss dissipation. Based on the SOC rate of parallel connected battery cells, the switches in the equalization circuit are controlled to change the equivalent series impedance of the parallel branch, which regulates the current flow to maximize SOC utilization. To verify the method, operations of 4 parallel-connected 18650 Li-ion battery cells with 3.7V-2.6Ah individually are simulated on Matlab/Simulink. The results show that the SOCs are balanced within 1% difference with less power dissipation over the conventional method.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.50-52
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• 2019

Dynamic resistance equalization is a viable technique to balance SOC of cells in a parallel-connected battery configuration due to high equalization performance, simplicity and low-cost. However, an inappropriate design of the equalization resistor can degrade the equalization performance and increase the power loss. This paper proposes an optimization process to design the equalization resistors to minimize power loss and equalization error. The simulation results show that the optimally designed resistor significantly enhance the performance in comparison with the conventional fixed-resistor equalization.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.350-352
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• 2007

Modularized charge equalization converter for HEV lithium-ion battery cells is proposed in this paper, in which intra-module and inter-module charge equalization can be achieved at the same time. For intra-module charge equalization, the conventional flyback DC/DC converters of low power and small size are employed, in which all of the primary sides are coupled in parallel for selective charge of the specific under charged cell within the module. For inter-module charge equalization, the flyback DC/DC converters are also added, in which all the secondary windings are electrically linked in parallel for automatic charge balancing among the modules. An engineering sample of forty cells hiring the proposed cell balancing scheme is implemented and its experimental result shows that the proposed modularized charge equalization circuit has good cell balancing performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.7
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• pp.32-38
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• 2012

In this paper, to eliminate intersymbol interference of the received signal due to multipath propagation, a parallel equalization algorithm using two error estimation functions is proposed. In the proposed algorithm, multilevel two-dimensional signals are considered as equivalent binary signals, then error signals are estimated using the sigmoid nonlinearity effective at the initial phase equalization and threshold nonlinearity with high steady-state performance. The two errors are scaled by a weight depending on the relative accuracy of the two error estimations, then two filters are updated differentially. As a result, the combined output of two filters was to be the optimum value, fast convergence at initial stage of equalization and low steady-state error level were achieved at the same time thanks to the combining effect of two operation modes smoothly. Usefulness of the proposed algorithm was verified and compared with the conventional method through computer simulations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.11
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• pp.1377-1383
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• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

• Journal of Power Electronics
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• v.9 no.3
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• pp.472-480
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• 2009

In this paper, a charge equalization converter with parallel-connected primary windings of transformers is proposed. The proposed work effectively balances the voltage among Lithium-Ion battery cells despite each battery cell has low voltage gap compared with its state of charge (SOC). The principle of the proposed work is that the equalizing energy from all battery strings moves to the lowest voltage battery through the isolated dc/dc converter controlled by the corresponding solid state relay switch. For this research a prototype of four Lithium-Ion battery cells is optimally designed and implemented, and experimental results show that the proposed method has excellent cell balancing performance.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.274-276
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• 2008

This paper proposes an individual charge equalization converter using selective two current paths for series connected lithium-ion battery strings. In the proposed equalizer, a central equalization converter acting as a controllable current source is sequentially connected in parallel with individual batteries through an array of cell selection switches. A flyback converter with a modified rectifier realizes a controllable current source. A central equalization converter is shared by every battery cells through the cell selection switch, instead of a dedicated charge equalizer for each cell. With this configuration, although the proposed equalizer has one dc-dc converter, individual charge equalization can be effectively achieved for the each cell in the strings. Furthermore, since the proposed equalizer would not allocate the separated dc-dc converter to each cell, such that the implementation of great size reduction and low cost can be allowed. In this paper, an optimal power rating design guide is also employed to obtain a minimal balancing size while satisfying equalization requirements. A prototype for eight lithium-ion battery cells is optimally designed and implemented. Experimental results verify that the proposed equalization method has good cell balancing performance showing small size, and low cost.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.347-349
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• 2007

Charge equalization scheme for HEV lithium-ion battery system is proposed in this paper, where all the primary windings with in parallel bi-directional switches are coupled in series to provide the equalizing energy from the whole battery string to the specific under charged cells. Moreover, to realize minimized size of equalization circuit employing the proposed cell balancing scheme, the optimal power rating design rule according to equalization time and SOC distribution of imbalance is proposed. A prototype of HEV lithium-ion battery system of four cells shows the outstanding charge equalization performance while maintaining greatly reduced size of cell balancing circuit.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.256-258
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• 2007

A charge equalization converter with parallel-connected primary windings of transformers is proposed in digest. The proposed work effectively balance the voltage among Lithium-Ion battery cells despite each battery cell has low voltage gap compared with its SOC. The principle of the proposed work is that the equalizing energy from all battery strings moves to the lowest voltage battery through the isolated dc/dc converter controlled by the corresponding bi-directional switch. In this digest, a prototype of four Lithium-Ion battery cells is optimally designed and implemented, and experimental results show that the proposed method has excellent cell balancing performance.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.6
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• pp.492-499
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• 2000

In this paper, realization techniques of the parallel processing and the parallel network system for image processing are described. The parallel image processing system is constructed by the characterization of image processing and processor. Several problems are solved to achieve effective parallel processing and processor networking with the particular properties of image processing, which are reduction of communication quantity, equalization of load and delay depreciation on communication. A parallel image input device is developed for the flexible networking of parallel image processing. An abnormal region detection algorithm which is the basic function in machine vision is applied to evaluate the constructed parallel image processing system. The performance and effectiveness of the system are confirmed by experiments.