• Journal of Power Electronics
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• 제18권4호
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• pp.1255-1267
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• 2018

Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1676-1679
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• 2003

A perfect matching is the desire of antenna designers. In this paper, we improve the matching of antenna designing. In general, the efficiency of antennas has many improvements. In this paper, we choose to extend matching by adding the slots in the basic microstrip-fed rectangular slot antenna. We called it as "parasitic slots". The dominant characteristic of this addition is double efficient improvement matching and other characteristics of antenna are similar. It means that the microstrip-fed rectangular slot antenna with parasitic slots has all characteristics as same as the microstrip-fed rectangular slot antenna without parasitic slots. The antenna with parasitic slots has better matching better than the antenna without parasitic slots.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.1-5
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• 2000

This paper deals with the modeling and analysis of the high voltage flyback transformer (HVFBT) often utilized in small-sized high voltage DC power supplies. The parasitic capacitance of th HVFBT with the large turns of the secondary winding causes the undesirable parasitic resonance in the transient state which produces the high current stress and limits the switching frequency of the converter. In order to analyze this phenomenon the equivalent circuit model including the parasitic capacitance is derived and the frequency characteristics are provided. The parasitic resonance in the switching states is also investigated based on this equivalent circuit model. The derived model and analysis is finally validated through the SPICE simulation and experiments.

• 대한전자공학회논문지
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• 제25권1호
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.

• Parasites, Hosts and Diseases
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• 제54권4호
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• pp.407-414
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• 2016

Malaria remains a serious public health problem in Shandong Province, China; therefore, it is important to explore the characteristics of the current malaria prevalence situation in the province. In this study, data of malaria cases reported in Shandong during 2012-2014 were analyzed, and Plasmodium species were confirmed by smear microscopy and nested-PCR. A total of 374 malaria cases were reported, 80.8% of which were reported from 6 prefectures. Of all cases, P. falciparum was dominant (81.3%), followed by P. vivax (11.8%); P. ovale and P. malariae together accounted for 6.4% of cases. Notably, for the first time since 2012, no indigenous case had been reported in Shandong Province, a situation that continued through 2014. Total 95.2% of cases were imported from Africa. The ratio of male/female was 92.5:1, and 96.8% of cases occurred in people 20-54 years of age. Farmers or laborers represented 77.5% of cases. No significant trends of monthly pattern were found in the reported cases. All patients were in good condition after treatment, except for 3 who died. These results indicate that imported malaria has increased significantly since 2012 in Shandong Province, especially for P. falciparum, and there is an emergence of species diversity.

• 한국산업정보학회논문지
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• 제21권1호
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• pp.1-6
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• 2016

본 논문에서는 기생 트랜지스터를 억제하여 대기 전류를 낮춰 기동전류를 개선한 수직 PNP 트랜지스터의 특성을 소개한다. 기생 효과를 억제하기 위해, 회로 변경 없이 "DN+ 링크"를 사용하여 기생 PNP 트랜지스터를 억제 시킨 수직 PNP 트랜지스터를 설계하였으며, 표준 IC 프로세서를 이용한 LDO 레귤레이터를 제작했다. 제작된 기생 PNP 트랜지스터의 hFE 가 기존의 18에서 0.9로 감소하였다. 개선된 "DN+ 링크" 구조 수직 PNP 트랜지스터로 제작된 LDO 레귤레이터의 기동 전류는 기존의 기동 전류 90mA에서 32mA 로 감소되었다. 이로 인해 대기상태에서 저 소비전력을 구현한 LDO 레귤레이터를 개발하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 추계학술대회 논문집
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• pp.13-16
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• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• 반도체디스플레이기술학회지
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• 제21권4호
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• pp.45-49
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• 2022

Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.208-211
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• 1999

Abstract - Electrical characteristics or asymmetric n-MOSFET's with different source and drain geometry are experimently investigated using test structures having various gate width. Saturation drain current and resistance in linear region are estimated by a simple schematic model, which consists of conventional device having parasitic resistor. A comparison of experimental results of symmetric and asymmetric devices gives the parasitic resistance caused by abnormal device structure. The suggested model shows good agreement with the measured drain current for both forward- and reverse-modes.

• 전력전자학회논문지
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• 제20권2호
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• pp.137-143
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• 2015

This paper presents the intra capacitance modeling based on the winding method and section bobbin for CM choke capable of EMI attenuation of broad bands from lower to higher frequency bands and high frequency type common-mode choke capable of EMI attenuation of high frequency band used in the EMI Block of LED-TV SMPS. The case of high frequency type CM choke can be explained by the parasitic capacitance of three types of CM choke. The winding method of section bobbin type is smaller than the others. The first resonant frequency of the proposed CM choke tends to increase as the parasitic capacitance becomes small and its impedance characteristics improved performance as the first resonant frequency increases. The CM chokes of the proposed section bobbin type shows that in the future, the method may have practical use in LED/LCD-TV SMPS and in several applications, such as LED lighting, adapters, and so on.