• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.1057-1060
• /
• 1998

Power Dissipation and circuit speed become the most importance parameters in VLSI system maximum power dissipation for VLSI system design. We remodeled CMOS inverter according to the operating region, saturation region or linear regin, and calculate maximum power dissipation point of CMOS inverter. The result of proposed maximum power dissipation model compared with those from SPICE simulation which results that the proposed maximum power dissipation model has the error rate within 10% to SPICE simulation.

• Journal of IKEEE
• /
• v.8 no.2 s.15
• /
• pp.181-185
• /
• 2004

This paper reduces power dissipation with the minimum switching activity of functional units that have many operators. Therefore, it has more effects of power dissipation that operator dissipation to reduce power dissipation of whole circuit preferentially. This paper proposes an algorithm that minimize power dissipation in functional units operations that affect much as power dissipation in VLSI circuit. The algorithm has scheduled operands using power library that has information of all operands. The power library upgrades information of input data in each control step about all inputs of functional units and the information is used at scheduling process. Therefore, the power dissipation is minimized by functional units inputs in optimized data. This paper has applied algorithm that proposed for minimizing power dissipation to functional unit in high level synthesis. The result of experiment has effect of maximum 9.4 % for minimizing power dissipation.

• Proceedings of the KSR Conference
• /
• 2011.10a
• /
• pp.3092-3098
• /
• 2011

This paper deals with analysis of measuring power dissipation when Maglev is running. With the various running scenarios for Maglev, power dissipation was measured and a comparative analysis of it and wheel-on rails were carried out. The purpose of this paper is to confirm the efficiency and economics on operation of Maglev and reflect detail design later. When the running scenarios of Maglev are the status of landing on and levitation, running at rated acceleration and deceleration and according to changes of velocity, the power dissipation was measured. The measured results are analyzed considering with apparent electric power and active power, reactive power and power factor etc. Due to the limited test track condition, it is very limited to compare and analyze Maglev and general trains. Nevertheless, It is a task of great significance to identify the efficiency and economics on operating Maglev through the results of measuring power dissipation. In the future, measuring power dissipation through more various scenarios will be carried out, and the results will be reflected the design.

• ETRI Journal
• /
• v.44 no.3
• /
• pp.491-503
• /
• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.18 no.4
• /
• pp.169-175
• /
• 2018

Recently, power dissipation issue is very significant not only in high-end modern processors but also in embedded systems and mobile devices. Based on the power dissipation, hardware and software designers can correctly find the power/performance tradeoffs. Most power analysis tools calculate power dissipation when chip layout or floor planning are finished. In this paper, a trace-driven simulator that can interact with power analysis tool for an embedded microprocessor has been developed. Using MiBench embedded benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation which is faster than the conventional tools.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.101-104
• /
• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• Transactions of Materials Processing
• /
• v.7 no.5
• /
• pp.450-458
• /
• 1998

The high temperature deformation behavior of Al 5083 alloy has been studied in the temperature range of 350 to 520 ${\circ}C$ and strain rate range of 0.2 to 3.0/sec by torsion test. The strain rate sensitivity(m) of the material was evaluated and used for estabilishing power dissipation maps following the dynamic material model. These maps show the variation of efficiency of power dissipation(${\eta}$=2m/(2m+1)) with temperature and strain rate. Hot restoration of dynamic recrystallization (DRX) was analyzed from the flow curve, deformed microstructure, and processing maps during hot deformation. Also, the effect of deformation strain on the efficiency of power dissipation of the alloy was analysed using the processing maps. Moreover relationship between the hot-ductility and efficiency of power dissipation of the alloy depending on thmperature and strain rate was studied using the Zener-Hollomon parameter(Z=${\varepsilon}$exp(Q/RT) It is found that the maximum efficiency of power dissipation for DRX in Al 5083 alloy is about 74.6 pct at the strain of 0.2. The strain rate and temperature at which the efficiency peak occurred in the DRX domain is found to be ∼0.1/sec and ∼450${\circ}C$ respectively.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.6
• /
• pp.128-133
• /
• 1994

This paper proposes a new TTL-to-CMOS converter which has low power dissipation. This converter has no static power dissipation for typical TTL output voltage levels. The simulatio result shows that the power dissipation is reduced to about 1/20 of conventional level converter using CMOS inverters. It also has hysteresis due to the positive feedback which makes the converter noise immune. The logic threshold voltages in the hysteresis characteristic can be optimized by changing the size ratios of the transistors.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.2
• /
• pp.251-256
• /
• 2017

Recently, multicore processor system is widely adopted not only in general purpose computers but also in embedded systems and mobile devices in order to improve performance. Since the power dissipation issue of multicore processor system is very significant, it must be estimated accurately in the early design stage. In this paper, a fast power analysis tool for a high performance multicore processor based on the trace-driven simulator has been developed. To achieve it, the power dissipation of each hardware unit per core are added. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation per instruction.

• Journal of Digital Contents Society
• /
• v.9 no.3
• /
• pp.471-481
• /
• 2008

Test scheduling considering power dissipation is an effective technique to reduce the testing time of complex SoCs and to enhance fault coverage under limitation of allowed maximum power dissipation. In this paper, a modeling technique of test resources and a test scheduling algorithm for efficient test procedures are proposed and confirmed. For test resources modeling, two methods are described. One is to use the maximum point and next maximum point of power dissipation in test resources, the other one is to model test resources by partitioning of them. A novel heuristic test scheduling algorithm, using the extended-tree-growing-graph for generation of maximum embedded cores usable simultaneously by using relations between test resources and cores and power-dissipation-changing-graph for power optimization, is presented and compared with conventional algorithms to verify its efficiency.