• Nuclear Engineering and Technology
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• v.39 no.6
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• pp.717-724
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• 2007

A measurement-based time-domain noise simulation of radiation detector-preamplifier (front-end) noise in nuclear spectroscopy is described. The time-domain noise simulation was performed by generating "noise random numbers" using Monte Carlo's inverse method. The probability of unpredictable noise was derived from the empirical cumulative distribution function via the sampled noise, which was measured from a preamplifier output. Results of the simulated noise were investigated as functions of time, frequency, and statistical domains. Noise behavior was evaluated using the signal wave-shaping function, and was compared with the actual noise. Similarities between the response characteristics of the simulated and the actual preamplifier output noises were found. The simulated noise and the computed nuclear pulse signal were also combined to generate a simulated preamplifier output signal. Such simulated output signals could be used in nuclear spectroscopy to determine energy resolution degradation from front-end noise effect.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.72-79
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• 2003

Classical designs of optical transimpedance preamplifier for p-i-n photodiode receiver circuits generally employ common source transimpedance input stages. In this paper, we explore the design of a class of current-mode optical transimpedance preamplifier based upon common gate input stages. A feature of current-mode optical transimpedance preamplifier is high gain and high bandwidth. The bandwidth of the transimpedance preamplifier can also be increased by the capacitive peaking technique. In this paper we included the development and application of a circuit analysis technique based on the minimum noise. We develop a general formulation of the technique, illustrate its use on a number of circuit examples, and apply it to the design and optimization of the low-noise transimpedance amplifier. Using the noise minimization method and the capacitive peaking technique we designed a transimpedance preamplifier with low noise, high-speed current-mode transimpedance preamplifier with a 1.57GHz bandwidth, and a 2.34K transimpedance gain, a 470nA input noise current. The proposed preamplifier consumes 16.84mW from a 3.3V power supply.

• Journal of Sensor Science and Technology
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• v.31 no.2
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• pp.120-124
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• 2022

With advancements in underwater stealth technology for naval vessels, new sensor configurations for detecting targets have been attracting increased attention. Latest underwater mines adopt multiple sensor configurations that include electric field sensors to detect targets and to help acquire accurate ignition time. An underwater electric field sensor consists of a pair of electrodes, signal processing unit, and preamplifier. For detecting underwater electric fields, the preamplifier requires low-noise amplification at ultra-low frequency bands. In this paper, the specific requirements for low-noise preamplifiers are discussed along with the experimental results of various setups of matched transistors and chopper stabilized operational amplifiers. The results showed that noise characteristics at ultra-low frequency bands were affected significantly by the voltage noise density of the chopper amplifier and the number of matched transistors used for differential amplification. The fabricated preamplifier was operated within normal design parameters, which was verified by testing its gain, phase, and linearity.

• Journal of IKEEE
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• v.25 no.2
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• pp.309-314
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• 2021

The proposed preamplifier for the static random access memory reduces the time required for the sense amplifier enable during the read operation by 55%, which leads to a significant speed up the total spped. This is attirbuted to the novel circuit techqniue that cancels out the transistor mismatch which is induced by the process variation. In addition, a selective enable circuit for preamplifier circuit is proposed, so the proposed preamplifier is enabled only when it is required. Accordingly the energy overhead is limited below 4.45%.

• Korean Journal of Optics and Photonics
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• v.5 no.2
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• pp.333-339
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• 1994

We fabricated a single mode fiber pigtailed PIN-preamplifier front-end receiver module for the high speed optical receiver. Hybrid method was used to integrate GaInAs PIN photodiode and transimpedance type GaAs preamplifier. The capacitance and the diameter of light receiving area of PIN photodiode were 0.35 pF and $20{\mu}m$ respectively. The -3 dB cut-off frequency of PIN-preamplifier module was above 2 GHz, and the sensitivity of the module at 2.5 Gbps NRZ $(PRBS=2^{23}-1)$ signal was -25.2 dBm at $10^{-9}$ BER. > BER.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.322-329
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• 2007

A single pixel photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has been designed with $0.18{\mu}m$ triple-well CMOS process. The designed single pixel for readout chip is able to be operated by single supply voltage to simplify digital X-ray image sensor module and a preamplifier which is consist of folded cascode CMOS operational amplifier has been designed to enlarge signal voltage(${\Delta}Vs$), the output voltage of preamplifier. And an externally tunable threshold voltage generator circuit which generates threshold voltage in the readout chip has been newly proposed against the conventional external threshold voltage supply. In addition, A dark current compensation circuit for reducing dark current noise from photo diode is proposed and 15bit LFSR(Linear Feedback Shift Resister) Counter which is able to have high counting frequency and small layout area is designed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.330-336
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• 2007

A single pixel photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has tern designed with $0.18{\mu}m$ triple-well CMOS process. The designed single pixel for readout chip is able to be operated by single supply voltage to simplify digital X-ray image sensor module and a preamplifier which is consist of folded cascode CMOS operational amplifier has been designed to enlarge signal voltage(${\Delta}Vs$), the output voltage of preamplifier. And an externally tunable threshold voltage generator circuit which generates threshold voltage in the readout chip has been newly proposed against the conventional external threshold voltage supply. In addition, A dark current compensation circuit for reducing dark current noise from photo diode is proposed and 15bit LFSR(Linear Feedback Shift Resister) Counter which is able to have high counting frequency and small layout area is designed.

• Proceedings of the KOSOMBE Conference
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• v.1998 no.11
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• pp.209-210
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• 1998

Noise characteristics of preamplifier, the most essential part of on-chip signal processing circuitry for the active semiconductor neural probe, is the important factor determining the overall signal-to-noise-ratio (SNR). We present a systematic design method for the optimization of SNR, based on the spectral characteristics of the electrode, circuit noise and extracelluar action potential. Analytical expression is derived to calculate total output noise power. Output SNR of 2-stage CMOS preamplifier is tailored to meet the given specification while the layout area is minimized.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.34-38
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• 2000

This paper describes design, fabrication, and performance of an ultra-high-speed and low-noise MMIC (Monolithic Microwave Integrated Circuit) preamplifier for a 10 Gb/s optical receiver. The transimpedance type 3-stage MMIC preamplifier for ultra-high-speed and low-noise was designed using an AlGaAs/InGaAs/GaAs P-HEMTs(Pseudomorphic High Electron Mobility Transistors) with 0.15${\mu}{\textrm}{m}$ length T-shaped gate. To obtain broadband characteristics, we used the inductor peaking technique, and the gate width was optimized for low noise performance. Measurements reveal that the fabricated preamplifier has the high transimpedance gain of 60 ㏈Ω and 9.15 ㎓ bandwidth with the noise figure of less than 3.9 ㏈.

• Journal of IKEEE
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• v.17 no.3
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• pp.275-283
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• 2013

In this paper, a 8bit 10Ms/s CMOS Folding and Interpolation analog-to-digital convertor is proposed. The architecture of the proposed ADC is based on a Folding & Interpolation using FR(Folding Rate)=8, NFB(Number of Folding Block)=4, IR(Interpolation Rate)=8. The proposed ADC adopts a preamplifier sharing method to decrease the number of preamplifier by half comparing to the conventional ones. This chip has been fabricated with a 0.35[um] CMOS technology. The effective chip area is $1.8[mm]{\times}2.11[mm]$ and it consumes 20[mA] at 3.3 power supply with 10[MHz] clock. The INL is -0.57, +0.61 [LSB] and DNL is -0.4, +0.51 [LSB]. The SFDR is 48.9[dB] and SNDR is 47.9[dB](ENOB 7.6b) when the input frequency is 100[kHz] at 10[MHz] conversion rate.