• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.4
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• pp.200-207
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• 2004

This paper presents a simple and fast delay metric RC-class interconnects under saturated ramp inputs. The RC delay metric under saturated ramp inputs, called FDM(Fast Delay Metric), can estimate delay times at an arbitrary node using a simple closed-form expression and is extended from delay metric under step input easily As compared with similar techniques proposed in previous researches, it is shown that the FDM technique complexity for a similar accuracy. As the number of circuit nodes increases, there will be a significant difference in estimation times of RC delay between the previous techniques based on two circuit moments and the FDM which do not depend on circuit moments.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.5
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• pp.193-193
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• 2003

This Paper analyses several model-order reduction methods and then proposes an improved n model and a new delay calculation method to be used in analyzing RC-class interconnects, which does not involve moment calculation processes. The proposed delay calculation method has been derived by combining the unproved $\pi$ model, the concept of effective capacitance and Elmore delay. This method has an advantage in that it can be applied in the calculation of end-to-end delay as well as incremental delay.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.5
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• pp.193-200
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• 2003

This Paper analyses several model-order reduction methods and then proposes an improved n model and a new delay calculation method to be used in analyzing RC-class interconnects, which does not involve moment calculation processes. The proposed delay calculation method has been derived by combining the unproved $\pi$ model, the concept of effective capacitance and Elmore delay. This method has an advantage in that it can be applied in the calculation of end-to-end delay as well as incremental delay.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.209-219
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• 1995

As a new algorithm for RC tree delay estimation, we propose a $\tau$-model of the driver and a moment propagation method. The $\tau$-model represents the driver as a Thevenin equivalent circuit which has a one-time-constant voltage source and a linear resistor. The new driver model estimates the input voltage waveform applied to the RC more accurately than the k-factor model or the 2-piece waveform model. Compared with Elmore method, which is a lst-order approximation, the moment propagation method, which uses $\pi$-model loads to calculate the moments of the voltage waveform on each node of RC trees, gives more accurate results by performing higher-order approximations with the same simple tree walking algorithm. In addition, for the instability problem which is common to all the approximation methods using the moment matching technique, we propose a heuristic method which guarantees a stable and accureate 2nd order approximation. The proposed driver model and the moment propagation method give an accureacy close to SPICE results and more than 1000 times speedup over circuit level simulations for RC trees and FPGA interconnects in which the interconnect delay is dominant.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.7
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• pp.299-303
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• 2005

This paper proposes an analytic method can estimate delay time considering crosstalk noise at an arbitrary node of RC-class interconnects under saturated ramp input using a simple closed-form expression. In the case of single interconnects, algebraic expression presented in existent research can estimate delay time under ramp input using delay time under step input, and we applied it to estimate delay time considering crosstalk noise. As the result, we can provide a intuitive analysis about signal integrity of circuits that include crosstalk noise reducing computational complexity significantly.

• Journal of the Korean Institute of Telematics and Electronics
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• v.4 no.4
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• pp.13-18
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• 1967

Since all the poles of the open circuit voltage transfer function of the trigonometric, linear, passive RC circuits exist on the negative real axis of s-plane, its transient response to the unit step input is monotonic. This satisfies the necessary conditions for the applicability of Elmore's method which had been developed originally for the transient analysis of lumped circuit in computing the rise time and delay time of the trigonometric distributed RC circuits. This paper describes the computing method of rise and delay times of the trigonometric distributed RC circuit. The analysis shows that the transient response of this kind circuit depends only upon the time constant and distance angle $\theta$. As $\theta$ is increased, the rise and delay titles are increased non-linearly.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.573-576
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• 2004

This paper proposes an analytic method that can estimate delay time considering crosstalk noise at an arbitrary node of RC-class interconnects under saturated ramp input using a simple closed-form expression. In the case of single interconnects, algebraic expression presented in existent research can estimate delay time under ramp input using delay time under step input, and we applied it to estimate delay time considering crosstalk noise. As the result, we can provide a intuitive analysis about signal integrity of circuits that include crosstalk noise reducing computational complexity significantly.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.13-18
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• 1978

A delay switching PLL (DSPLL) is proposed for improvement of the frequency acquisition Performance (pull-in range) while keeping a narrow bandwidth LPF. It has, between the phase detector and the LPF, just a simple RC delay circuit, a switch and another phase detector controlling the switching time. For the common second order PLL, the pull-in capability of the DSPLL is analyzed approximately, without considering additive white noise effect, and verified experimentally. It is shown that the delay switching extends the pull-in range significantly, as much as a half of lock-range. At the phase tracking mode, the delay switching does not function, to make the DSPLL be a normal PLL.

• Environmental Engineering Research
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• v.20 no.2
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• pp.155-161
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• 2015

Experimental research shows that the nitric oxides ($NO_X$) concentration track at the outlet of selective catalytic reduction (SCR) catalyst with a transient variation of Adblue dosage has a time delay and it features a characteristic of resistance-capacitance (RC). The phenomenon brings obstacles to get the simultaneously $NO_X$ expected to be reduced and equi-molar ammonia available to SCR reaction, which finally inhibits $NO_X$ conversion efficiency. Generally, engine loads change frequently, which triggers a rapid changing of Adblue dosage, and it aggravates the air quality that are caused by $NO_X$ emission and ammonia slip. In order to increase the conversion efficiency of $NO_X$ and avoid secondary pollution, the paper gives a comprehensive analysis of the SCR system and tells readers the key factors that affect time delay and RC characteristics. Accordingly, a map of time delay is established and a solution method for time constant and proportional constant is carried out. Finally, the paper accurately describes the input-output state relation of SCR system by using "variable RC model with time delay". The model can be used for a real-time correction of Adblue dosage, which can increase the conversion efficiency of $NO_X$ in SCR system and avoid secondary pollution forming. Obviously, the results of the work discover an avenue for the SCR control strategy.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.875-880
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• 2019

A RC4 stream cipher is widely used for security applications such as IEEE 802.11 WEP, IEEE 802.11i TKIP and so on, because it can be simply implemented to dedicated circuits and achieve a high-speed encryption. RC4 is also used for systems with limited resources like IoT, but there are performance limitations. RC4 consists of two stages, KSA and PRGA. KSA performs initialization and randomization of S-box and K-box and PRGA produces cipher texts using the randomized S-box. In this paper, we initialize the S-box and K-box in the randomization of the KSA stage to reduce the initialization delay. In the randomization, we use clusters to process swap operation between elements of S-box in parallel and can generate two cipher texts per clock. The proposed RC4 cipher hardware can initialize S-box and K-box without any delay and achieves about 2 times to 6 times improvement in KSA randomization and key stream generation.