• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.31-33
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• 2001

전통적으로 스캔 설계 법칙 검사는 게이트 레벨에서 수행되었다. 그러나 RTL 설계와 합성 도구의 사용이 일반화되면서 게이트 레벨 회로의 검사는 합성 단계에서의 최적화와 스캔 설계 법칙 위배를 정정한 후의 최적화가 필요하여 많은 시간이 소요된다. RTL에서의 스캔 설계 법칙 검사는 이러한 문제를 해결할 수 있으며, 이것이 본 논문의 주제이다. 본 논문에서는 스캔 설계 법칙의 위배를 RTL 설계에서 검사할 수 있는 기법을 제안한다. 이 기법은 효과적인 설계 과정에 의해 설계 시간 을 단축할 수 있을 것이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.78-85
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• 2008

This paper presents a high-level design methodology applied on an SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the poject with working Verilog RTL models in hands, which we later compared our SystemC models to real Verilog RTL models. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.2
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• pp.99-107
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• 2003

This paper proposes a design for testability (DFT) and testability analysis method for register-transfer level (RTL) circuits. The proposed method executes testability analysis - controllability and observability - on the RTL circuit and determines the insertion points to enhance the testability. Then with the associated priority based on the testability, we insert only a few of the test multiplexers resulting in minimized area overhead. Experimental results shows a higher fault coverage and a shorter test generation time than the scan method. Also, the proposed method takes a shorter test application time required.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.799-802
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• 1998

본 논무은 HLS에서 CPLD 조건식을 고려한 RTL바인딩 기술로서 HDL로 기술된 회로의 스케쥴링을 한후 모듈 연산 간격을 고려하여 합당한 모듈을 선택하고 스케쥴링과 할당을 수행한 후 주어진 조건식에 맞도록 CPLD를 선정한다. 또한 할당된 결과의 모듈을 CPLD 내부의 CLB의 크기를 고려하여 부울식을 분할하고 최적의 CLB를 사용하여 회로를 구현할 수 있도록 binding 알고리즘을 제안하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2181-2186
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• 2006

In this paper, a RTL binding technique for CPLD constraint is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in used CLB.

• Journal of the Korean Society of Tobacco Science
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• v.22 no.2
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• pp.164-169
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• 2000

The reconstituted tobacco leaves(RTL) playa major part in the control of the low density and tar cigarette. Reconstituted tobacco manufactured by the papermaking process has much higher filling power than homogenized tobacco manufactured by slurry and rolling process. Fragile reconstituted tobaccos are liable to lead to small particles detrimental for filling power so they must be properly flexible. This work was conducted to determine the effect of CaCO$_3$ addition in paper-making process on the filling power and the flexibility of the reconstituted tobacco and to obtain the fundamental informations for improving the quality of domestic reconstituted tobacco. We analyzed the wood fiber species, the filler level, the fiber length, the fineness level and observed the surface of the RTL. From the obtained results, we could determine that foreign reconstituted tobacco was manufactured by blending softwood with hardwood and over 8% of calcium carbonate at the addition level. The domestic RTL has much higher fine fiber level by 23.2 % than that of foreign, so the refining treatment process and the condition must be reoptimized for the improvement of RTL quality.

• Journal of Radiation Protection and Research
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• v.43 no.3
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• pp.114-119
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• 2018

Background: The retrospective dosimetry using RTL quartz can be improved by information for an optical sensitivity of sample connected with the equivalent dose determination. Materials and Methods: The quartz sample from a volcanic rock of Japan was used. After correcting the thermal quenching effect, RTL peaks of quartz were separated by the CGCD method cooperated with the general order kinetics. The number of overlapped glow peaks were ascertained by the $T_m-T_{stop}$ method. The optical sensitivity was examined by comparing the change of intensity on RTL glow peaks measured after exposure to light from a solar simulator with various illumination times. Results and Discussion: Seven glow peaks appeared to be overlapped on the RTL glow curve. The general order kinetics model was appropriate to separate glow peaks. After exposure to light from a solar simulator from a few minutes to 416 hr, the signals for peaks P4 and P5 decayed following the form of $f(t)=a_1e^{-{\lambda}1t}$, while the signals for peaks P6 and P7 decayed by the form of $f(t) = a_1e^{-{\lambda}1t}+a_2e^{-{\lambda}2t}+a_3e^{-{\lambda}3t}$. Conclusion: For dosimetric peaks, the times taken to reduce the RTL signal to half of its initial value were 70 sec for the peak P4, 54 s for the peak P5, 9,840 sec for the peak P6 and 26,580 sec for the peak P7, respectively. We conclude that the optical sensitivity of peaks P4, and P5 gives much higher than that of peaks P6 and P7.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.555-562
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• 2008

In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.1-6
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• 2006

In this paper, a RTL binding technique and low power technology mapping consider CPLD is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD consider low power. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in the power consumption by 43% comparing with that of non application algorithm.

• The Magazine of the IEIE
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• v.29 no.1
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• pp.66-72
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• 2002

VLSI 기술의 발전은 보다 많은 양의 로직을 단일 칩에 집적 가능하게 했고, 이는 System-on-a-chip 시대의 도래를 가능하게 했다. System-on-a-chip을 가능하게 하기 위해서는 많은 종류의 IP (Intellectual Property)가 필요하고, 공정 변환을 쉽게 하기 위해서는 합성이 가능한 RTL 설계가 절실히 요구된다. 본 논문은 이러한 요구에 부응하기 위해서 hard macro 형태의 기존의 IP로 부터 합성 가능한 IP를 자동 생성해 주는 ART(Automatic RTL Translation)로 명명된 기법에 관한 것이다. 제안된 ART 기법을 이용하여 80C52 호환의 8-bit MCU(Micro-controller Unit)의 합성 가능한 RTL model을 자동 생성하였고, 개발된 Soft IP를 이용하여 TCP/IP 전용 MCU를 표함해서 다양한 제품들을 개발하였다.