• International journal of advanced smart convergence
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• 제11권1호
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• pp.28-35
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• 2022

This paper presents a performance evaluation of real-time Linux for industrial real-time platforms. On industrial platforms, multicore processors are popular due to their work distribution efficiency and cost-effectiveness. Multicore processors, however, are not designed for applications with real-time constraints, and their performance capabilities depend on their core configurations. In order to assess the feasibility of a multicore processor for real-time applications, we conduct a performance evaluation of a general processor and a low-power processor to provide an experimental environment of real-time Linux on both Xenomai and RT-preempt considering the multicore configuration. The real-time performance is evaluated through scheduling latency and in an environment with loads on the CPU, memory, and network to consider an actual situation. The results show a difference between a low-power and a general-purpose processor, but from developer's point of view, it shows that the low-power processor is a proper solution to accommodate low power situations.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제6권2호
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• pp.113-119
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• 2000

본 논문에서는 주기억장치 데이타베이스의 특성을 반영하여 시간제약조건을 처리할 수 있는 실시간 주기억장치 데이타베이스시스템을 위한 질의 처리기를 설계하고 구현한다. 제안된 질의 처리기는 메타 데이타베이스를 이용하여 시간제약을 갖는 실시간 데이타를 유지 관리한다. 응용 프로그램의 작성을 위해서 CLI를 지원하고 있으며, 이를 확장한 확장 CLI와 저장 CLI를 지원하여 확장 CLI를 이용하여 실시간 트랜잭션의 정보를 CLI를 사용으로 표현할 수 있도록 하였고, 빈번하게 수행되는 트랜잭션을 지원하기 위해 저장 CLI를 지원한다. 제안된 질의 처리기는 주기억장치 실시간 데이타베이스 관리시스템의 질의처리기로 구현하였으며, 성능평가를 통해서 시스템의 질의처리 능력과 실시간 데이타의 효율적인 관리를 통해서 종료시한을 만족하는 실시간 트랜잭션의 비율이 증가됨을 보였다.

• 한국정밀공학회지
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• 제16권1호통권94호
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• pp.61-67
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• 1999

A laser Doppler vibrometer based on the laser heterodyne interferometry is employed to measure the vibration velocity of vibrating objects. In this paper, we propose a real time analog signal processor of a laser Doppler vibrometer to reduce the degradation of Doppler signals mainly caused by environmental noises. In the proposed real time signal processor of an laser Doppler vibrometer, a pre-processor and a logical motion direction detector are designed to reduce the detection errors of the object motion direction. Also, a noise detection and rejection circuit is designed to reject the unfiltered noises.

• 한국정보전자통신기술학회논문지
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• 제2권3호
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1990년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 26-27 Oct. 1990
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• pp.1032-1036
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• 1990

This paper describes a system which enables a real-time measurement of 2-D water flow field. One distinctive feature of our system is that velocity vectors of water flow are obtained from the movement of tracer particles at video rate. In order to enable a fast measurement a real time video processor and two Digital Signal Processor(TMS32OC25) are employed. The real-time video processor extracts contours of tracer particles in order to reduce the amount of image data to be processed. And two DSP(Digital Signal Processor) analyse the correlation of every tracer paticle in the consecutive two images to obtain the velocity distribution of water flow.

• International journal of advanced smart convergence
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• 제8권1호
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• pp.9-17
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• 2019

In this article, we present a performance enhancement scheme for mobile applications by adopting persistent memory. The proposed scheme supports the deadline guarantee of real-time applications like a video player, and also provides reasonable performances for non-real-time applications. To do so, we analyze the program execution path of mobile software platforms and find two sources of unpredictable time delays that make the deadline-guarantee of real-time applications difficult. The first is the irregular activation of garbage collection in flash storage and the second is the blocking and time-slice based scheduling used in mobile platforms. We resolve these two issues by adopting high performance persistent memory as the storage of real-time applications. By maintaining real-time applications and their data in persistent memory, I/O latency can become predictable because persistent memory does not need garbage collection. Also, we present a new scheduler that exclusively allocates a processor core to a real-time application. Although processor cycles can be wasted while a real-time application performs I/O, we depict that the processor utilization is not degraded significantly due to the acceleration of I/O by adopting persistent memory. Simulation experiments show that the proposed scheme improves the deadline misses of real-time applications by 90% in comparison with the legacy I/O scheme used in mobile systems.

• 대한임베디드공학회논문지
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• 제10권6호
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• pp.363-372
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• 2015

Recent some SoC FPGA Releases that integrate ARM processor and FPGA fabric show better performance compared to the ASIC SoC used in typical embedded image processing system. In this study, using the above advantages, we implement a SoC FPGA-based Real-Time Object Recognition and Tracking System. In our system, the video input and output, image preprocessing process, and background subtraction processing were implemented in FPGA logics. And the object recognition and tracking processes were implemented in ARM processor-based programs. Our system provides the processing performance of 5.3 fps for the SVGA video input. This is about 79 times faster processing power than software approach based on the Nios II Soft-core processor, and about 4 times faster than approach based the HPS processor. Consequently, if the object recognition and tracking system takes a design structure combined with the FPGA logic and HPS processor-based processes of recent SoC FPGA Releases, then the real-time processing is possible because the processing speed is improved than the system that be handled only by the software approach.

• 한국HCI학회:학술대회논문집
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• 한국HCI학회 2008년도 학술대회 1부
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• pp.230-235
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• 2008

본 논문에서는 ARM 프로세서로 설계된 VoWiFi 단말기에서 광대역 음성 서비스를 가능하게 하기 위한 방법으로 ITU-T 표준 코텍인 G.729.1을 실시간으로 구현하고 그 성능을 평가한다. 실시간 G.729.1 코덱 구현은 C 코드 최적화 및 코덱 알고리즘의 고속화를 근간으로 한다. 이렇게 최적화된 코덱의 성능은 VoWiFi 단말기내에서 ARM 프로세서가 요구하는CPU 동작 시간으로 평가된다. 실험 결과, ARM926EJ를 사용하여 최적화된 G.729.1 코덱이 실시간으로 동작함을 확인할 수 있으며, 기존의 G.729에 비해 넓은 대역폭의 음성 전송이 가능함을 보일 수 있다.

• 제어로봇시스템학회논문지
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• 제3권6호
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• pp.626-631
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• 1997

This paper represents the design of a real-time image preprocessing system. The preprocessing system performs hardware-wise mask operations and thresholding operations at the speed of camera output single rate. The preprocessing system consists of the preprocessing board and the main processing board. The preprocessing board includes preprocessing unit that includes a $5\times5$ mask processor and LUT, and can perform mask and threshold operations in real-time. To achieve high-resolution image input data($20485\timesn$), the preprocessing board has a linescan camera interface. The main processing board includes the image processor unit and main processor unit. The image processor unit is equipped with TI's TMS320C32 DSP and can perform image processing algorithms at high speed. The main processor unit controls the operation of total system. The proposed system is faster than the conventional CPU based system.

• 전자공학회논문지CI
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• 제40권2호
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• pp.17-25
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• 2003

본 논문에서는 상태 변수 표현 방법에 따른 알고리즘 분할을 통해 2차원 웨이브렛 변환 연산을 실시간으로 처리할 수 있는 프로세서 구조를 제안하였다. 제안된 프로세서 구조는 영상입력에 대하여 행, 열 방향을 동시에 고려하여 데이터 플로우 방식으로 처리함으로써 중간적인 결과의 메모리 저장 및 읽기에 소요되는 전달 지연 시간을 감소할 수 있어 실시간 처리에 적합한 VLSI 구조이다. 필터의 길이를 K라할 때 프로세서는 내부에 4개의 곱셈기, 4개의 덧셈기 및 NK-N 크기의 메모리를 가지는 등의 하드웨어 복잡도가 낮아 웹 카메라 서버와 같은 내장형의 응용에 매우 적합한 구조이고, 쉽게 어레이 구조로 확장할 수 있어 고성능을 요구하는 다양한 영상 처리 응용에도 사용 가능하다.