• Title/Summary/Keyword: Reconfigurable Peripheral

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Wired/Wireless LED Lighting Communication Using Reconfigurable Peripheral Unit (재구성형 주변장치유닛을 사용한 유무선 LED 조명 통신)

  • Yoo, Sehoon;Gong, Jungchul;Kim, Kichul
    • Journal of IKEEE
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    • v.17 no.4
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    • pp.407-417
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    • 2013
  • In this paper, a reconfigurable peripheral unit for LED lighting communication is presented. Embedded lighting devices require various communication protocols. Usually, serial communication protocols and lighting control communication protocols such as DALI, DMX512, UART, SPI, IrDA, etc. are used in lighting devices. When the requirements of communication protocols are satisfied with separate IPs, the cost and the power consumption can considerably increase. We propose a reconfigurable communication peripheral unit which uses analysis of signal formats of the protocols. The gate count of the reconfigurable peripheral unit uses only 57% of the gate count of the separate implementation. Also, in this paper, a mapping table based DALI-ZigBee interfacing method for flexible lighting network configurations is proposed. Using this method, various DALI-ZigBee network systems can be easily set up. An LED lighting system platform is implemented to verify the operation of the DALI-ZigBee interfacing method. The reconfigurable peripheral unit and the DALI-ZigBee interfacing method can be efficiently used to implement various wired/wireless lighting communication systems.

Performance evaluation using BER/SNR of wearable fabric reconfigurable beam-steering antenna for On/Off-body communication systems (On/Off-body 통신시스템을 위한 직물소재 웨어러블 재구성 빔 스티어링 안테나의 BER/SNR 성능 검증)

  • Kang, Seonghun;Jeong, Sangsoo;Jung, Chang Won
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.7
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    • pp.4842-4848
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    • 2015
  • This paper presents a comparison of communication performance between the reconfigurable beam-steering antenna and the omni-directional (loop) antenna during standstill and walking motion. Both omni-directional and reconfigurable antennas were manufactured on the same fabric (${\varepsilon}_r=1.35$, $tqn{\delta}=0.02$) substrate and operated around 5 GHz band. The reconfigurable antenna was designed to steer the beam directions. To implement the beam-steering capability, the antenna used two PIN diodes. The measured peak gains were 5.9-6.6 dBi and the overall half power beam width (HPBW) was $102^{\circ}$. In order to compare the communication efficiency, both the bit error rate (BER) and the signal-to-noise ratio (SNR) were measured using a GNU Radio Companion software tool and user software radio peripheral (USRP) devices. The measurement were performed when both antennas were standstill and walking motion in an antenna chamber as well as in a smart home environment. From these results, the performances of the reconfigurable beam steering antenna outperformed that of the loop antenna. In addition, in terms of communication efficiencies, in an antenna chamber was better than in a smart home environment. In terms of movement of antennas, standstill state has better results than walking motion state.

Performance analysis of SNR and BER for radiation pattern reconfigurable antenna (인체 부착용 방사패턴 재구성 안테나의 SNR 및 BER 성능 분석)

  • Lee, Chang Min;Jung, Chang Won
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.6
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    • pp.4125-4130
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    • 2015
  • This paper presents the communication performance for the radiation pattern reconfigurable antenna in the wearable device measuring bio signal (temperature, blood pressure, pulse etc.) of human body. The operational frequency is 2.4 - 2.5 GHz, which covers Bluetooth communication bandwidth. The maximum gain of the antennas is 1.96 dBi. The proposed antenna is efficiently transmitting and receiving signal by generating two opposite beam directions using two RF switches (PIN diode). Also, we investigated how radiation pattern changes according to three angles ($30^{\circ}$, $90^{\circ}$, $150^{\circ}$) of Top Loading. In this paper, we measured and compared the SNR (Signal-to-Noise Ratio) and BER (Bit Error Rate) performances of the proposed antennas in the condition between an ideal environment of anechoic chamber and smart house existing practical electromagnetic interferences (Universal Software Radio Peripheral, USRP). Throughout the comparing the results of the measurement of two cases, we found that the SNR is degraded over 5dB in average and BER is increased over ten times in maximum, therefore, it is confirmed that the error rate of receiving signal is increased. The measured results of SNR and BER value in this paper able to expect the performance degrading by the interference from the electromagnetic devices.

Design of UHF Band Microstrip Antenna for Recovering Resonant Frequency and Return Loss Automatically (UHF 대역 공진 주파수 및 반사 손실 오토튜닝 마이크로스트립 안테나 설계)

  • Kim, Young-Ro;Kim, Yong-Hyu;Hur, Myung-Joon;Woo, Jong-Myung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.3
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    • pp.219-232
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    • 2013
  • This paper presents a microstrip antenna which recovers its resonant frequency and impedance shifted automatically by the approach of other objects such as hands. This can be used for telemetry sensor applications in the ultrahigh frequency(UHF) industrial, scientific, and medical(ISM) band. It is the key element that an frequency-reconfigurable antenna could be electrically controlled. This antenna is miniaturized by loading the folded plates at both radiating edges, and varactor diodes are installed between the radiating edges and the ground plane to control the resonant frequency by adjusting the DC bias asymmetrically. Using this voltage-controlled antenna and the micro controller peripheral circuits of reading the returned level, the antenna is designed and fabricated which recovers its resonant frequency and impedance automatically. Designed frequency auto recovering antenna is conformed to be recovered within a few seconds when the resonant frequency and impedance are shifted by the approach of other objects such as hand, metal plate, dielectric and so on.

Hardware Approach to Fuzzy Inference―ASIC and RISC―

  • Watanabe, Hiroyuki
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 1993.06a
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    • pp.975-976
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    • 1993
  • This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

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