• Journal of Computing Science and Engineering
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• v.2 no.3
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• pp.301-320
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• 2008

Partial redundancy elimination (PRE) is an interesting compiler optimization because of its effectiveness and generality. Among many PRE algorithms, the one in static single assignment form (SSAPRE) has benefits over other bit-vector-based PRE algorithms. It preserves the properties of the SSA form after PRE and exploits the sparsity of the SSA form, resulting in reduced analysis and optimization time. This paper presents a practical improvement of the SSAPRE algorithm that further reduces the analysis and optimization time. The underlying idea is removing unnecessary ${\Phi}$'s during the ${\Phi}$-Insertion phase that is the first step of SSAPRE. We classify the expressions into three categories: confined expressions, local expressions, and the others. We show that unnecessary ${\Phi}$'s for confined and local expressions can be easily detected and removed. We implement our locality-based SSAPRE algorithm in a C compiler and evaluate its effectiveness with 20 applications from SPEC benchmark suites. In our measurements, on average 91 of ${\Phi}$'s identified by the original demand-driven SSAPRE algorithm are unnecessary for PRE. Pruning these unnecessary ${\Phi}$'s in the ${\Phi}$-Insertion phase makes our locality-based SSAPRE algorithm 1.8 times faster, on average, than the original SSAPRE algorithm.

• The KIPS Transactions:PartA
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• v.13A no.6 s.103
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• pp.489-494
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• 2006

This paper improves the algorithms for Speculative Partial Redundancy Elimination(SPRE) proposed by Knoop et al. This research brings up an issue concerning a field to which SPRE cannot be applied, and suggests a solution to the problem. The Improved SPRE algorithm performs the execution speed optimization based on the information on the execution frequency from profiling and the memory space optimization.

• Journal of KIISE
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• v.44 no.9
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• pp.976-985
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• 2017

Wireless mesh network (WMN) is a promising technology for building a cost-effective and easily-deployed wireless networking infrastructure. To efficiently utilize limited radio resources in WMNs, packet transmissions (particularly, redundant packet transmissions) should be carefully managed. We therefore propose a lightweight traffic redundancy elimination (LTRE) scheme to reduce redundant packet transmissions in software-defined wireless mesh networks (SD-WMNs). In LTRE, the controller determines the optimal path of each packet to maximize the amount of traffic reduction. In addition, LTRE employs three novel techniques: 1) machine learning (ML)-based information request, 2) ID-based source routing, and 3) popularity-aware cache update. Simulation results show that LTRE can significantly reduce the traffic overhead by 18.34% to 48.89%.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.8
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• pp.1046-1054
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• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability. The developed hardware prototype can be utilized for analyzing the basic operation and performance improvement of MMC according to the modulation and redundancy operation scheme. It also can be utilize to analyze the basic operational characteristics of HVDC system based on MMC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.7
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• pp.930-939
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• 2021

In recent years, the use of broadband bandwidth and redundant links for stable transmission in networks has resulted in excessive energy consumption and reduced transmission efficiency. In this paper, we propose an optimization algorithm that reduces the number of transmission links and minimizes transmission energy by removing redundant traffic in networks where traffic redundancy is allowed. The optimization algorithm proposed in this paper uses the meta-heuristic method using Tabu search algorithm. The proposed optimization algorithm minimizes transmission energy by designing a neighborhood generation method that efficiently routes overlapping traffic. The performance evaluation of the proposed optimization algorithm was performed in terms of the number of links used to transmit all traffic generated in the network and the transmission energy consumed. From the performance evaluation results, it was confirmed that the proposed algorithm is superior to other algorithms previously proposed.

• Journal of Institute of Control, Robotics and Systems
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• v.12 no.12
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• pp.1241-1248
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• 2006

In high reliability systems for industrial network such as railway signal system, fieldbus protocols have been known to satisfy the real-time and fault tolerant requirements. But, the application of fieldbus has been limited due to the high cost of hardware and software, and the difficulty in interfacing with multi-vendor products. Therefore, as an alternative to fieldbus, the computer network technology, especially Ethernet(IEEE 802.3), is being adapted to the industrial network. In this paper, we propose a switched Ethernet based railway signal system because of its very promising prospect for industrial application due to the elimination of uncertainties in the network operation. In addition, we propose the redundancy architecture for the reliability of network components. More specifically, this paper presents an analytical performance evaluation of switched Ethernet for railway signal system, and shows experimental evaluation of redundancy architecture.

• The Journal of Korean Institute of Information Technology
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• v.16 no.12
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• pp.25-30
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• 2018

It is extremely lacking and urgently required that the method of constructing the Gene Regulatory Network (GRN) from RNA-Sequencing data (RNA-Seq) because of Big-Data and GRN in Big-Data has obtained substantial observation as the interactions among relevant featured genes and their regulations. We propose newly the computational comparative feature patterns selection method by implementing a minimum-redundancy maximum-relevancy (MRMR) filter the support vector machine-recursive feature elimination (SVM-RFE) with Intensity-dependent normalization (DEGSEQ) as a preprocessor for emphasizing equal preciseness in RNA-seq in Big-Data. We found out the proposed algorithm might be more scalable and convenient because of all libraries in R package and be more improved in terms of the time consuming in Big-Data and minimum-redundancy maximum-relevancy of a set of feature patterns at the same time.

• The KIPS Transactions:PartD
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• v.14D no.2
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• pp.217-224
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• 2007

In order to determine the value and type statically. CTOC uses the SSA Form which separates the variable according to assignment. The SSA Form is widely being used as the intermediate expression of the compiler for data flow analysis as well as code optimization. However, the conventional SSA Form is more associated with variables rather than expressions. Accordingly, the redundant expressions are eliminated to optimize expressions of the SSA From. This paper defines the partial redundant expression to obtain a more optimized code and also implements the technique for eliminating such expressions.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.6
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• pp.26-30
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• 1977

Redundancies in the Calculation of DFT and FFT are analized and new algorithms are proposed which are capable of reducing the machine time by a considerable amount. New extensions of T.D C.F. and T.D.F.T. are given for the discrete case which permit a deeper insights for the techniques of digital signal Proessing i. e. Discrete Fourier Transform, Convolution Sum and Correlation sequences.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11a
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• pp.321-324
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• 2003

본 논문에서는 코드 최적화를 위하여 계산적으로나 수명적으로 제한이 없는 희소 코드 모션 알고리즘을 제안한다. 이 알고리즘은 지나친 레지스터의 사용을 막기 위하여 불필요한 코드 모션을 억제한다. 또한, 본 논문에서는 기존 알고리즘의 술어의 의미가 명확하지 않은 것을 개선하였고 노드 단위 분석과 명령어 단위 분석을 혼용했기 때문에 발생하는 모호함도 개선하였다. 따라서, 제안한 알고리즘은 불필요하게 중복된 수식이나 배정문의 수행을 피하게 함으로써, 프로그램의 불필요한 재계산이나 재실행을 하지 않게 하여 프로그램의 능률 및 실행시간을 향상시킨다.