• ETRI Journal
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• v.30 no.4
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• pp.624-626
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• 2008

Excessively high temperature deteriorates the reliability and increases the leakage power consumption of microprocessors. The register file, known as one of the hottest functional units in microprocessors, incurs frequent dynamic thermal management operations for thermal control. In this letter, we adopt the banked register file scheme, which was originally proposed to reduce dynamic power consumption. By simply modifying the register file structure, the temperature in the register file was reduced dramatically, resulting in 13.37% performance improvement and 10.49% total processor leakage reduction.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.121-130
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• 2011

Recent research indicates that transient errors will increasingly become a critical concern in microprocessor design. As embedded processors are widely used in reliability-critical or noisy environments, it is necessary to develop cost-effective fault-tolerant techniques to protect processors against transient errors. The register file is one of the critical components that can significantly affect microprocessor system reliability, since registers are typically accessed very frequently, and transient errors in registers can be easily propagated to functional units or the memory system, leading to silent data error (SDC) or system crash. This paper focuses on investigating the impact of register file soft errors on system reliability and developing cost-effective techniques to improve the register file immunity to soft errors. This paper proposes the register vulnerability factor (RVF) concept to characterize the probability that register transient errors can escape the register file and thus potentially affect system reliability. We propose an approach to compute the RVF based on register access patterns. In this paper, we also propose two compiler-directed techniques and a hybrid approach to improve register file reliability cost-effectively by lowering the RVF value. Our experiments indicate that on average, RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly, without sacrificing the register value integrity.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.7
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• pp.1-10
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• 1992

This paper gives on overview of register windowing structure and presents advantages and limitations. Based on these advantages and disadvantages, an original approach for the design of large register file is presented, analyzed and compared with existing approaches. The advantages and disadvantages of this new approach to register file design are discussed, and conditions under which it works better than the existing approaches are outlined. Design tradeoffs are examined in an analytic and empirical study, and the results of which are summarized in the conclusion of this paper.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.12
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• pp.540-551
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• 2008

Today's microprocessor designs are not free from temperature as well as power consumption. As processor technology scales down, an on-chip circuitry increases power density, which incurs excessive temperature (hotspot) problem. To tackle thermal problems cost-effectively, Dynamic Thermal Management (DTM) has been suggested: DTM techniques have benefits of thermal reliability and cooling cost. However, they require trade-off between thermal control and performance loss. This paper proposes a dual integer register file structure to minimize the performance degradation due to DTM invocations. In on-chip thermal control, the most important functional unit is an integer register file. It is the hotspot unit because of frequent read and write data accesses. The proposed dual integer register file migrates read data accesses by adding an extra register file, thus reduces per-unit dynamic power dissipation. As a result, the proposed structure completely eliminates localized hotspots in the integer register file, resulting in much less performance degradation by average 13.35% (maximum 18%) improvement compared to the conventional DTM architecture.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.148-152
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• 2009

Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.

• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.3
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• pp.128-135
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• 2010

Recently complexity of embedded software cause to be used real-time operating system (RTOS) to implement various functions in the embedded system. And also, according to requirement of complex functions in embedded systems, the number as well as complexity of tasks get increased continuously. In case that many tasks collaborated in a microprocessor, context switching time between tasks is a overhead waisting a CPU resource. Therefore the time of task context switching is an important factor that affects performance of RTOS. In this paper, we concentrate on the improvement of task context switch for reducing overhead and achieving fast response time in RTOS. To achieve these goal, we suggest multiple register files and task context switching algorithm. By reducing the context switch overhead, we try to ease scheduling and assure fast response times in multitasking environment. As a result, the context switch overhead decreased by 8~16% depend on the number of register files, and some task set which are not schedulable with single register file are schedulable due to that decrease with multiple register files.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1211-1220
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• 1990

This paper describes and implements a design method of register allocation as a required module of RISC compiler systems. It compiles a C program to a machine-independent intermediate language, translates each variable into symbolic register. After local allocation process for the symbolic registers, global register allocation is executed by applying the graph coloring algorithm. This register allocation phase is designed for a system with the large register file like RISC machines.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.229-234
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• 2007

In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrix-vector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1165-1168
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• 1998

This paper describes a 72-word by 32-bit 2-read/1-write multi-port register file, which is suitable for 32-bit RISC/DSP microprocessors. To minimize area and achieve high speed, advanced single-ended sense amplifiers are used. Each part of circuit is optimized at transistor level. The verification of functionality and timing is performed using HSPICE simulations. After modeling and validating the circuit at transistor level, it was laid out in a 0.6um 1-poly 3-metal layer CMOS technology. The simulation results show maximum operating frequency is 179MHz in worst case conditions. It contains 27,326 transistors and the size is 3.02mm by 2.20mm.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.29-32
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• 2010

공정이 미세화 될수록 프로세서 상에서의 thermal management는 점점 중요해지고 있다. 칩의 온도가 임계 온도를 넘어 손상되거나, 시스템이 불능이 되는 상황을 방지하기 위해 그 동안 많은 기법들이 소개되어 왔다. 하지만 이러한 기법들은 시스템 전체를 끄거나 느려지게 함으로써 상당한 양의 성능 저하를 가져왔다. 이 논문에서는 프로세서의 가장 중요한 Hotspot인 Register File의 온도 관리를 위한 기법으로 Periodic Mapping을 제안하고, 이를 기존의 기법들과 비교해 본다.