• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5B
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• pp.286-294
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• 2007

In ASIP design, compiler is required for performance evaluation of processors being designed. The design of machine specific compiler is time consuming. This paper presents the system which generates C compiler from MDL descriptions. Compiler generation using MDL can support user retargetability and concurrency between compiler design and processor design. However, it must overcome semantics gap between compiler and machine. To handle this problem, the proposed system maps behavioral descriptions to library which contains abstract behavior for each tree pattern. Using mapped instructions and information on register file usage, the proposed system generates back-end interface function of the compiler. Generated compilers, for MIPS R3000, ARM9 cores, have been proved by application programs written in C code.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11a
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• pp.431-434
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• 2003

과거 임베디드 시스템은 산업용 같은 특수한 경우와 여러 전자 제품에서 눈에 뛰지 않는 형태로 사용이 되어 왔지만 최근 들어 정보통신 분야가 발전하고 가격 대 성능비가 우수한 Microcontroller 와 CPU 들이 등장하면서 더욱 더 각광을 받기 시작했다. 이들의 개발환경은 C 언어와 어셈블리어가 주를 차지하고 있는데 개발상의 많은 장점 때문에 C 언어를 선택하여 사용하고 있지만 target machine 의 C 컴파일러가 전부 제공되지 않고 일부 machine 만 제공되고 있기 때문에 C 언어의 사용은 아직 제한적이다. 이에 본 논문에서는 Retargetable Compiler 인 LCC 를 이용하여 임베디드용 machine 에 대해 retargeting 이 가능하도록 LCC 를 개선시키고자 한다.

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.275-288
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• 2006

Rapid design space exploration is crucial to customizing embedded system design for exploiting the application behavior. As the time-to-market becomes a key concern of the design, the approach based on an application specific instruction-set processor (ASIP) is considered more seriously as one alternative design methodology. In this approach, the instruction set architecture (ISA) for a target processor is frequently modified to best fit the application with regard to code size and speed. Two goals of this paper is to introduce our new retargetable compiler and how it has been used in ASIP-based design space exploration for a popular digital signal processing (DSP) application. Newly developed retargetable compiler provides not only the functionality of previous retargetable compilers but also visualizes the features of the application program and profiles it so that it can help architecture designers and application programmers to insert new application specific instructions into target architecture for performance increase. Given an initial RISC-style ISA for the target processor, we characterized the application code and incrementally updated the ISA with more application specific instructions to give the compiler a better chance to optimize assembly code for the application. We get 32% performance increase and 20% program size reduction using 6 audio codec specific instructions from retargetable compiler. Our experimental results manifest a glimpse of evidence that a higgly retargetable compiler is essential to rapidly prototype a new ASIP for a specific application.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.17-18
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• 2009

This paper shows our empirical comparison result between two retargetable compilers, GCC and SoarGen. SoarGen is our retargetable compiler. According to our experimental result, using SoarGen for targeting ODALRISC is proved to be easier and faster than using GCC. The average retarget time of the SoarGen is much less than the retarget time of the GCC.

• The KIPS Transactions:PartA
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• v.16A no.4
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• pp.245-254
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• 2009

With the increasing adoption of embedded processors, the need of developing compilers for the embedded processors with timely manner is also growing. Retargeting has been adopted as a viable approach to constructing new compilers by modifying the back-end of an existing compiler. This paper proposes a test suite generation system for testing retargetable C compilers. The proposed system generates the test suite using the grammar coverage concept. Generally, the size of the test suite satisfying the grammar coverage of the source language is very large. Hence, the proposed system also provides the facility to reduce the size of the test suite. According to the experimental result, the reduced test suite can detect 75% of the compiler faults detected by the original test suite though the size of the reduced test suite is only 10% of that of the original test suite in average. This result indicates that the reduction technique proposed in this paper can be effectively used in the prior phase of the development procedure of the embedded compilers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.1
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• pp.1-9
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• 2013

This thesis proposes an automatic instruction extension system that utilizes retargetable compiler, based on MDL, to design an ASIP optimized for application. The proposed system uses information gathered from the application program to find all possible expandable instruction candidates. Expandable instruction candidates acquire the realization characteristics through hardware library. The system chooses instruction set and optimizes processor structure satisfying constraints on the bases of hardware characteristics and increase in execution speed. To confirm the efficiency of the proposed system, automatic instruction extension system was performed using various benchmark applications. The proposed system acquired optimized instruction set and processor structure, which are expanded from the commercial version of ARM9TDMI. Experimental results show that number of execution cycle has been reduced by 33.5% when compared to conventional version of ARM9TDMI, while area has been slightly increased.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.913-921
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• 2007

Retargetable compiler which generates executable code for a target processor and performance profiler are required to design a processor optimized for a specific application. This paper presents an architecture exploration methodology based on ADL (Architecture Description Language). We synthesized instruction set and optimized processor structure using information extracted from application program. The information of operation sequences executed frequently and register usage are used for processor optimization. Architecture exploration has been performed for JPEG encoder to show the effectiveness of the system. The ASIP designed using the proposed method shows 1.97 times better performance.

• The Journal of the Korea Contents Association
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• v.8 no.12
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• pp.63-71
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• 2008

Recently, together with a new advent of embedded processor developed to support specific application area, and it evolution, a new study of software development to support the embedded processor and its commercial use has been revitalized. Specially, In a mobile device that is built-in embedded processor, software management is as important as hardware management for the limited power/energy. In this paper, we suggest that the code generation technique considering the energy dissipation through the verified retargetable compiler backend tool, EXPRESSION. For this goals, we describes the efficient code generation patterns and showed the variable performance results.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10b
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• pp.575-579
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• 2006

컴파일러에 결함이 있다는 것은 곧 잘못된 코드를 생성한다는 것을 의미하므로 양질의 컴파일러 구성은 양질의 소프트웨어 생산을 위한 기본 요구조건이 된다. 임베디드 시스템이 널리 사용되면서 더욱 다양하고 복잡한 임베디드 프로세서가 개발되었고 이는 새로이 설계된 프로세서를 위한 새로운 컴파일러 개발의 필요를 야기하고 있다. 본 논문에서는 프로그램의 중간 표현을 기반으로 하는 효율적인 테스팅 방법을 제안한다. 언어의 구문 규칙을 모두 사용하는 테스트 케이스를 통해 컴파일러를 테스트하는 방법이 이미 연구되었으나, 기존의 소스 코드 수준의 방법으로는 테스트 케이스의 중복성이 존재하는 단점이 있다. 본 논문에서는 중간 표현의 구문 규칙을 이용해서 중복된 테스트 케이스를 제거하여 테스팅 효율을 증가시킬 수 있음을 기술한다. 또한 본 논문에서 제안하는 방법을 GCC의 중간 언어인 RTL에 적용한 예를 통해 설명한다.

• Proceedings of the Korea Society for Simulation Conference
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• 2003.06a
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• pp.79-84
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• 2003

이 논문은 빠른 ASIP(application specific instruction processor) 평가를 위한 재적응성을 가진 컴파일러/시뮬레이터 환경에 대해 이야기한다. ASIP의 성능은 하드웨어 구조뿐만 아니라, 수행되는 응용 소프트웨어에 영향을 받기 때문에, 높은 성능의 ASIP 개발을 위해서는 컴파일러 및 시뮬레이터의 개발이 선행되어야 한다. 그러나 다양한 ASIP 구조에 따라 적합한 고성능의 컴파일러/시뮬레이터를 만드는 일은 매우 시간 소모적인 일이 될 뿐만 아니라, 오류가 발생하기도 쉽다. 본 논문에서는 HiXR2라는 ADL(architecture description language)을 이용하여 명령어 구조를 기술하고 이를 바탕으로 컴파일러와 시뮬레이터를 자동 생성하였다. HiXR2의 재적응성 및 생성된 컴파일러/시뮬레이터의 정확성을 검증하기 위하여 ARM9 프로세서와 CalmRISC32 프로세서 구조를 각각 기술하고, 각각에 대하여 응용프로그램 코드를 컴파일 및 시뮬레이션 하는 예제를 보였다.