• Proceeding of EDISON Challenge
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• 2017.03a
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• pp.372-375
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• 2017

Metal-oxide-semiconductor Field-Effect transistor (MOSFET)을 대체할 기술로서 제안된 Schottky Barrier MOSFET (SB-MOSFET)가 제시되고 있다. 본 연구에서는 SB-MOSFET와 MOSFET을 다양한 소자 파라미터를 변화시킴으로서 양자역학적 전하수송 계산을 바탕으로 특성을 분석한다. MOSFET과 SB-MOSFET은 채널 두께 ($T_{Si}$)가 감소함에 따라 전류량은 증가하고 SS와 DIBL은 증가하였고 Overlap에서는 SS와 DIBL이 커지고 Underlap에서는 작아짐을 보였고 SB-MOSFET는 특히 그 폭이 컸다. 또한 SB 높이가 낮을수록 SB-MOSFET의 전류량이 증가하고 SS는 감소하였고 마찬가지로 Source와 Drain doping concentration이 낮을수록 MOSFET의 전류량은 증가하고 SS는 감소하였다. MOSFET과 SB-MOSFET의 경향은 대체로 비슷하나 변화량의 차이 등이 있었다.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.234-237
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• 2013

본 논문에서는 실리콘 나노선 구조를 갖는 모스펫 (Metal-Oxide-Semiconductor Field Effect Transistors, MOSFETs)과 쇼트키 장벽 트랜지스터 (Schottky-Barrier(SB) MOSFETs, SB-MOSFETs)의 전기적인 특성을 양자역학적 시뮬레이션 계산을 통해 비교하였다. 쇼트키 장벽 높이 (Schottky Barrier, ${\phi}_{SBH}$)에 따른 SB-MOSFETs의 터널링 특성을 분석하고, 소스/드레인 (S/D) 길이가 변함에 따라 달라지는 S/D 저항을 계산하여, ${\phi}_{SBH}$가 0eV인 SB-MOSFETs의 On과 Off $I_D$ 비율 ($I_{ON}/I_{OFF}$)이 MOSFETs보다 개선될 수 있음을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.21-27
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• 2009

In this work, Er-silicided SB-SOI nMOSFET and Pt-silicided SB-SOI pMOSFET have been fabricated to investigate the current-voltage characteristics of Schottky barrier SOI nMOS and pMOS at elevated temperature. The dominant current transport mechanism of SB nMOS and pMOS is discussed using the measurement results of the temperature dependence of drain current with gate voltages. It is observed that the drain current increases with the increase of operating temperature at low gate voltage due to the increase of thermal emission and tunneling current. But the drain current is decreased at high gate voltage due to the decrease of the drift current. It is observed that the ON/Off current ratio is decreased due to the increased tunneling current from the drain to channel region although the ON current is increased at elevated temperature. The threshold voltage variation with temperature is smaller and the subthreshold swing is larger in SB-SOI nMOS and pMOS than in SOI devices or in bulk MOSFETs.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.450-453
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• 2014

쇼트키 장벽 모스펫(Schottky barrier MOSFETs : SB-MOSFETs)은 SB높이(${\Phi}_B$)에 매우 민감하다. 그래서 ${\Phi}_B$를 줄이는 공정 방법에 대한 연구가 활발히 진행 중이다. 이러한 ${\Phi}_B$를 측정할 때, SB-MOSFETs에서가 아닌 SB 다이오드에서 측정이 이뤄지고 있다. 본 논문에서는 ${\Phi}_B$를 SB-MOSFETs에서 측정 할 수 있는 방법을 제안하고 전산모사를 통하여 채널의 길이와 두께, Overlap / Underlap 구조, 온도 등에 대한 의존성을 살펴 보았다. 그 결과 채널의 길이와 두께, Overlap / Underlap 구조에 따른 의존성은 없는 것으로 확인되었다. 하지만 20nm 이하의 채널의 소자에 대해서는 소스/드레인간 터널링 전류로 인해 정확한 ${\Phi}_B$ 측정이 불가능하였다. 그리고 저온에서 측정할 때 정확도가 높아짐을 확인하였다.

• Journal of Sensor Science and Technology
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• v.31 no.4
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• pp.271-277
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• 2022

We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the N_it distribution using TCAD simulation. As interface trap number density (N_it) increased, the threshold voltage increased while the drain current density decreased. Under N_it=5.0×10¹⁰ cm^-2 condition, the threshold voltage was 3.2 V for V_DS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the N_it distribution type, there was an increase in the subthreshold swing (SS) following an increase in N_it. Under U-shaped N_it distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Q_f) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.82-87
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• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.36-36
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• 2009

In this work, we describe a method to fabricate the Pt-silicided SB-MOSFETs with a n-type Silicon-On-Insulator (SOI) substrate as an active layer and demonstrate their electrical and structural properties. The fabricated SB-MOSFETs have novel structure and metal gate without sidewall. The gate oxide with a thickness of 7 nm was deposited by sputtering. Also, this fabrication processes were carried out below $500^{\circ}C$. As a result, Subthreshold swing value and on/off ratio of Fabricated SB MOSFETs was 70 [mV/dec] and $10^8$.

• Journal of Sensor Science and Technology
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• v.26 no.2
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• pp.79-84
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• 2017

The drain current of the SB MOSFET was analytically modeled by an equation composed of thermionic emission and tunneling with consideration of the image force lowering. The depletion region electron concentration was used to model the channel electron concentration for the tunneling current. The Schottky barrier width is dependent on the channel electron concentration. The drain current is changed by the gate oxide thickness and Schottky barrier height, but it is hardly changed by the doping concentration. For a GaN SB MOSFET with ITO source and drain electrodes, the calculated threshold voltage was 3.5 V which was similar to the measured value of 3.75 V and the calculated drain current was 1.2 times higher than the measured.

• Journal of Sensor Science and Technology
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• v.27 no.3
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• pp.150-155
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• 2018

Three different structures of GaN MOSFETs with trap distributions, trap levels, and densities were simulated, and its results were analyzed. Two of them are Schottky barrier MOSFETs(SB-MOSFETs): one with a p-type GaN body while the other is in the accumulation mode MOSFET with an undoped GaN body and regrown source/drain. The trap levels, distributions and densities were considered based on the measured or calculated properties. For the SB-MOSFET, the interface trap distribution affected the threshold voltage significantly, but had a relatively small influence on the subthreshold swing, while the bulk trap distribution affects the subthreshold swing more.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.210-214
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• 2016

In this paper, the decrease in the contact resistance of Ni germanide/Ge contact was studied as a function of the thickness of the antimony (Sb) interlayer for high performance Ge MOSFETs. Sb layers with various thickness of 2, 5, 8 and 12 nm were deposited by RF-Magnetron sputter on n-type Ge on Si wafers, followed by in situ deposition of 15nm-thick Ni film. The contact resistance of samples with the Sb interlayer was lower than that of the reference sample without the Sb interlayer. We found that the Sb interlayer can lower the contact resistance of Ni germanide/Ge contact but the reduction of contact resistance becomes saturated as the Sb interlayer thickness increases. The proposed method is useful for high performance n-channel Ge MOSFETs.