• Journal of KIISE:Computing Practices and Letters
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• v.16 no.7
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• pp.789-793
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• 2010

Recently, flash memory-based non-volatile cache (NVC) is emerging as an effective solution to enhance both I/O performance and energy consumption of storage systems. To get significant performance and energy gains by NVC, it would be better to use multi-level-cell (MLC) flash memories since it can provide a large capacity of NVC with low cost. However, the number of available program/erase cycles of MLC flash memory is smaller than that of single-level-cell (SLC) flash memory limiting the lifespan of NVC. To overcome such a limitation, SLC/MLC combined flash memory is a promising solution for NVC. In this paper, we propose an effective management scheme for heterogeneous SLC and MLC regions of the combined flash memory.

• The KIPS Transactions:PartA
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• v.15A no.6
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• pp.335-344
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• 2008

We propose an adaptive garbage collection technique for hybrid flash memory which has both SLC and MLC. Since SLC area is fast and MLC area has low cost, the proposed scheme utilizes the SLC area as log buffer and the MLC area as data block. Considering the high write cost of MLC flash, the garbage collection for the SLC log buffer moves a page into the MLC data block only when the page is cold or the page migration invokes a small cost. The other pages are moved within the SLC log buffer. Also it adjusts the parameter values which determine the operation of garbage collection adaptively considering I/O pattern. From the experiments, we can know that the proposed scheme provides better performance compared with the previous flash management schemes for the hybrid flash and finds the parameter values of garbage collection close to the optimal values.

• Journal of Advanced Navigation Technology
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• v.20 no.4
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• pp.321-328
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• 2016

Typical MLC NAND flash devices are considered less reliable than SLC NAND flash devices. Although raw bit error rate (RBER) of MLC flash had been considered approximately 1000times or more higher than that of SLC flash, recent research conducted on Google's data center shows that it is much lower than such expectation. Based on the research, we devised In Drive Data Duplication (IDDD) scheme that efficiently exploit MLC flash's sufficient capacity to improve its data reliability without structural complexity increment using SSD intrinsic firmware layer, and showed the data reliability expectation of MLC flash could be significantly higher than that of SLC flash from measured and calculated error rates. Even though RBER of SLC flash was lower than that of MLC flash in 44 out of 48 cases we studied, applying IDDD scheme, RBER of MLC flash was became lower than that of SLC in all 48 cases and uncorrectable bit error rate (UBER) of MLC flash was became lower than that of SLC flash in 45 out of 48 cases.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.107-116
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• 2016

Density of Phase-Change Memory (PCM) devices has been doubled through the employment of multi-level cell (MLC) technology. However, this doubled-capacity comes in the expense of severe performance degradation, as compared to the conventional single-level cell (SLC) PCM. This negative effect on the performance of the MLC PCM detracts from the potential benefits of the MLC PCM. This paper introduces an efficient way of minimizing the performance degradation while maximizing the capacity benefits of the MLC PCM. To this end, we propose a location-aware hybrid management of SLC and MLC in compressed PCM main memory systems. Our trace-driven simulations using real application workloads demonstrate that the proposed technique enhances the performance and energy consumption by 45.1% and 46.5%, respectively, on the average, over the conventional technique that only uses a MLC PCM.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.3
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• pp.134-138
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• 2009

We present a flash memory system with low cost and high performance for solid-state disk. The proposed flash system is constructed as a SLC with hot blocks and a MLC with cold blocks. Either the SLC or the MLC is selectively accessed on the basis of a position bit in a mapping table. Our results show that the system enables the SLC size to be reduced by about 80% relative to a conventional SLC while maintaining similar performance. And also, our system can improve a performance by above 60% comparing with a conventional MLC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.26-33
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• 2012

As the flash memory has increased the market share of data storage in imbedded system and occupied the most of area in a system, It has a profound impact on system reliability. Flash memory is divided NOR/NAND-type according to the cell array structure, and is classified as SLC(Single Level Cell)/MLC(Multi Level Cell) according to reference voltage. Although NAND-type flash memory is slower than NOR-type, but it has large capacity and low cost. Also, By the effect of demanding mobile market, MLC NAND-type is widely adopted for the purpose of the multimedia data storage. Accordingly, Importance of fault detection algorithm is increasing to ensure MLC NAND-type flash memory reliability. There are many researches about the testing algorithm used from traditional RAM to SLC flash memory and it detected a lot of errors. But the case of MLC flash memory, testing for fault detection, there was not much attempt. So, In this paper, Extend SLC NAND-type flash memory fault detection algorithm for testing MLC NAND-type flash memory and try to reduce these differences.

• Journal of KIISE
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• v.44 no.11
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• pp.1130-1137
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• 2017

The multi-leveling technique that stores multiple bits in a single memory cell has significantly improved the density of NAND flash memory along with shrinking processes. However, because of the side effects of the multi-leveling technique, the average write performance of MLC NAND flash memory is degraded more than twice that of SLC NAND flash memory. In this paper, we introduce existing cross-layer optimization techniques proposed to improve the performance of MLC NAND flash-based storages, and propose a new integration technique that overcomes the limitations of existing techniques by exploiting their complementarity. By fully exploiting the performance asymmetry in MLC NAND flash devices at the flash translation layer, the proposed technique can handle many write requests with the performance of SLC NAND flash devices, thus significantly improving the performance of NAND flash-based storages. Experimental results show that the proposed technique improves performance 39% on average over individual techniques.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.94-101
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• 2013

The market for NAND flash-based storage devices has grown significantly as they rapidly replace traditional disk-based storage devices. Heterogeneous NAND flash-based storage devices using both multi-level cell (MLC) and single-level cell (SLC) NAND flash memories are also actively researched since both types of memories complement each other. Heterogeneous NAND flash-based storage devices suffer from the overheads incurred by migration from SLC to MLC and garbage collection of SLC. This paper proposes a new flash translation layer (FTL) for heterogeneous NAND flash-based storage devices to reduce the overheads by utilizing SLC efficiently. The proposed FTL analyzes the access patterns of logical blocks and selects and stores only logical blocks expected to bring performance improvement in SLC. The experimental results show that the total execution time of heterogeneous NAND flash-based storage devices with our proposed FTL scheme is 35% shorter than that with the previously proposed best FTL scheme.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.357-359
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• 2018

최근 메모리 반도체 시장은 SD(Secure Digital) 메모리 카드, SSD(Solid State Drive)등의 보급률 증가로 메모리 반도체의 시장이 대규모로 증가하고 있다. 메모리 반도체는 개인용 컴퓨터 뿐만 아니라 스마프폰, 테플릿 PC, 교육용 임베디드 보드 등 다양한 산업에서 이용 되고 있다. 또한 메모리 반도체 생산 업체가 대규모로 메모리 반도체 산업에 투자하면서 메모리 반도체 시장은 대규모로 성장되었다. 플래시 메모리는 크게 NAND-Type과 NOR-Type으로 나뉘며 플로팅 게이트 셀의 전압의 따라 SLC(Single Level Cell)과 MLC(Multi Level Cell) 그리고 TLC(Triple Level Cell)로 구분 된다. SLC 및 MLC NAND-Type 플래시 메모리는 많은 연구가 진행되고 이용되고 있지만, TLC NAND-Tpye 플래시 메모리는 많은 연구가 진행되고 있지 않다. 본 논문에서는 기존에 제안된 SLC 및 MLC NAND-Type 플래시 메모리에서 제안된 큐브 패턴을 TLC NAND-Type 플래시 메모리에서 적용 가능한 큐브 패턴 및 알고리즘을 제안한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.36-42
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• 2016

In multi-level-cell based storage devices, TLC NAND has been employed solid state drive due to cost effectiveness. Since TLC has slow performance and low endurance compared with MLC, TLC based storage has adopted SLC buffer scheme to improve performance. To improve SLC buffer scheme, this paper proposes page overwriting method in SLC block. This method provides data updates without erase operation within a limited number. When SLC buffer area is filled up, FTL should execute copying valid pages and erasing it. The proposed method reduces erase counts by 50% or more compared with previous SLC buffer scheme. Simulation results show that the proposed SLC buffer overwrite method achieves 2 times write performance improvement.