• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.9-16
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• 2008

In this paper, a simple analytical model for deriving the threshold voltage of a short-gate SOI MESFET is suggested. Using the iteration method, the Poisson equation in the fully depleted silicon channel and the Laplace equation in the buried oxide region are solved two-dimensionally, Obtained potential distributions in each region are expressed in terms of fifth-order of $\chi$, where $\chi$ denotes the coordinate perpendicular to the silicon channel direction. From them, the bottom channel potential is used to describe the threshold voltage in a closed-form. Simulation results show the dependencies of the threshold voltage on the various device geometry parameters and applied bias voltages.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.217-222
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• 2003

A new two-dimensional analytical model for the potential distribution and drain-induced barrier lowering (DIBL) effect of fully depleted short-channel Silicon-on-insulator (SOI)-MESFET's has been presented in this paper. The two dimensional potential distribution functions in the active layer of the device is approximated as a simple parabolic function and the two-dimensional Poisson's equation has been solved with suitable boundary conditions to obtain the bottom potential at the Si/oxide layer interface. It is observed that for the SOI-MESFET's, as the gate-length is decreased below a certain limit, the bottom potential is increased and thus the channel barrier between the drain and source is reduced. The similar effect may also be observed by increasing the drain-source voltage if the device is operated in the near threshold or sub-threshold region. This is an electrostatic effect known as the drain-induced barrier lowering (DIBL) in the short-gate SOI-MESFET's. The model has been verified by comparing the results with that of the simulated one obtained by solving the 2-D Poisson's equation numerically by using the pde toolbox of the widely used software MATLAB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.25-32
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• 2005

In this paper, it is attempted to provide a unified explanation for typical short channel GaAs MESFET’s and SOI-structured Si JFET's behaviors such as: i) drain voltage-induced threshold voltage roll-off, ii) finite output ac resistance beyond the saturation, and iii) weak dependence of the drain saturation current on the channel length. Replacing the conventional GCA with a new assumption that is suggested in order to include the longitudinal field variation, and taking into account the channel current continuity and the field-dependent mobility, we can derive the two-dimensional potential in both depletion region and undepleted conducting channel. Obtained expressions for the threshold voltage and the drain current will be considerably accurate over the entire operating region. Moreover, in comparison with the conventional channel length shortening models, our model seems to be more reasonable in explaining the Early effect.